Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

Multiple quantum well self electro-optic effect devices for optoelectronic smart pixels

The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Organic integrated pixels fabricated by a full evaporation method

An organic integrated pixel consisting of an organic light-emitting diode driven by an organic thin-film field-effect transistor (OTFT) was fabricated by a full evaporation method oil a transparent glass substrate. The OTFT was designed as a top-gate Structure, and the insulator is composed of a double-layer polymer of Nylon 6 and Teflon to lower the operation voltage and the gate-leakage current, and improve the device stability. The field-effect mobility of the OTFT is more than 0.5 cm(2) V-1 s(-1), and the on/off ratio is larger than 10(3). The brightness of the pixel reached as large as 300 cd m(-2) at a driving current of 50 mu A.

Research on Q-Switched Nd : YAG laser engraving

IN this paper, the engraving process with Q-Switched Nd:YAG laser is investigated. High power density is the pre- requisition to vapor materials, and high repetition rate makes the engraving process highly efficient. An acousto- optic Q-Switch is applied in the cavity of CW 200 W Nd:YAG laser to achieve the high peak power density and the high pulse repetition rate. Different shape craters are formed in a patterned structure on the material surface when the laser beam irradiates on it by controlling power density, pulse repetition rate, pulse quantity and pulse interval. In addition, assisting oxygen gas is used for not only improving combustion to deepen the craters but also removing the plasma that generated on the top of craters. Off-focus length classified as negative and positive has a substantial effect on crater diameters. According to the message of rotating angle positions from material to be engraved and the information of graph pixels from computer, a special graph is imparted to the material by integrating the Q- Switched Nd:YAG laser with the computer graph manipulation and the numerically controlled worktable. The crater diameter depends on laser beam divergence and laser focal length. The crater diameter changes from 50 micrometers to 300 micrometers , and the maximum of crater depth reaches one millimeter.

A reliable phase unwrapping algorithm based on the local fitting plane and quality map

A fast and reliable phase unwrapping (PhU) algorithm, based on the local quality-guided fitting plane, is presented. Its framework depends on the basic plane-approximated assumption for phase values of local pixels and on the phase derivative variance (PDV) quality map. Compared with other existing popular unwrapping algorithms, the proposed algorithm demonstrated improved robustness and immunity to strong noise and high phase variations, given that the plane assumption for local phase is reasonably satisfied. Its effectiveness is demonstrated by computer-simulated and experimental results.

基于分支设置的质量导引相位展开算法

二维相位展开方法是近年来较为活跃、引起关注的一个研究课题，它在许多测量应用中有着重要的作用。尽管掩膜阻断算法在多个领域都有成功应用实例，该算法存在着固有的缺陷。为了克服掩膜阻断算法的缺陷，综合分支阻断方法和质量导引方法的优点，提出一种基于分支设置的质量导引相位展开新算法。它先以一个初始质量图来引导分支的设置，然后把分支对应的相位质量设置为最低，从而产生一个新的质量图，最后按新质量图来引导相位展开，并使用几个包裹相位图来验证此方法的有效性。计算机模拟相位图和实际相位图的相位展开结果表明，在存在复杂轮廓不连续

基于低速面阵CCD的正弦相位调制干涉测量

正弦相位调制(SPM)干涉测量技术用于表面形貌测量时, 需要帧速高于300 frame/s的图像传感器, 同时要求调制信号频率与图像传感器帧速成确定的整数倍关系。提出一种基于低速CCD(30 frame/s)的帧速可调的高速图像传感技术, 通过控制每帧像素总数提高CCD帧速, 研制出一种高帧速图像传感器, 帧速可达300～1600 frame/s, 且每帧大小连续可调。将该CCD传感器用于正弦相位调制干涉泰曼-格林干涉仪, 测量镀膜玻璃板表面形貌, 当CCD图像传感器的帧速与调制信号频率呈16, 8, 4

A high-speed image sensing technique with adjustable frame rate based on an ordinary CCD

In the sinusoidal phase modulating interferometer technique, the high-speed CCD is necessary to detect the interference signals. The reason of ordinary CCD's low frame rate was analyzed, and a novel high-speed image sensing technique with adjustable frame rate based on ail ordinary CCD was proposed. And the principle of the image sensor was analyzed. When the maximum frequency and channel bandwidth were constant, a custom high-speed sensor was designed by using the ordinary CCD under the control of the special driving circuit. The frame rate of the ordinary CCD has been enhanced by controlling the number of pixels of every frame; therefore, the ordinary of CCD can be used as the high frame rate image sensor with small amount of pixels. The multi-output high-speed image sensor has the deficiencies of low accuracy, and high cost, while the high-speed image senor with small number of pixels by using this technique can overcome theses faults. The light intensity varying with time was measured by using the image sensor. The frame rate was LIP to 1600 frame per second (f/s), and the size of every frame and the frame rate were adjustable. The correlation coefficient between the measurement result and the standard values were higher than 0.98026, and the relative error was lower than 0.53%. The experimental results show that this sensor is fit to the measurements of sinusoidal phase modulating interferometer technique. (c) 2007 Elsevier GmbH. All rights reserved.

二元振幅型面板用于光束空间整形

为了提高高功率激光系统的整体效率和充分利用光能,需要对前端注入的高斯光束进行空间整形,实现驱动器终端激光的均匀化输出。采用振幅型二元面板对激光光束进行空间强度整形,利用误差扩散法进行了理论设计,数值摸拟了整形效果,同时讨论了面板加工误差以及空间滤波器的小孔大小等因素带来的影响。根据理论设计,分别加工了反高斯透射率分布和抛物线透射率分布的二元面板,并进行了整形实验,实现了各自的整形功能,并做了误差分析。实验证明二元面板能对激光光束的空间强度分布实现了精确的整形。

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.