A block SPP algorithm for multidimensional tridiagonal equations with optimal message vector length

A parallel strategy for solving multidimensional tridiagonal equations is investigated in this paper. We present in detail an improved version of single parallel partition (SPP) algorithm in conjunction with message vectorization, which aggregates several communication messages into one to reduce the communication cost. We show the resulting block SPP can achieve good speedup for a wide range of message vector length (MVL), especially when the number of grid points in the divided direction is large. Instead of only using the largest possible MVL, we adopt numerical tests and modeling analysis to determine an optimal MVL so that significant improvement in speedup can be obtained.

On optimal message vector length for block single parallel partition algorithm in a three-dimensional ADI solver

It has long been recognized that many direct parallel tridiagonal solvers are only efficient for solving a single tridiagonal equation of large sizes, and they become inefficient when naively used in a three-dimensional ADI solver. In order to improve the parallel efficiency of an ADI solver using a direct parallel solver, we implement the single parallel partition (SPP) algorithm in conjunction with message vectorization, which aggregates several communication messages into one to reduce the communication costs. The measured performances show that the longest allowable message vector length (MVL) is not necessarily the best choice. To understand this observation and optimize the performance, we propose an improved model that takes the cache effect into consideration. The optimal MVL for achieving the best performance is shown to depend on number of processors and grid sizes. Similar dependence of the optimal MVL is also found for the popular block pipelined method.

A new year message from Chinese Science Bulletin

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-04-13T14:02:33Z No. of bitstreams: 1 A new year message from Chinese Science Bulletin.pdf: 888462 bytes, checksum: 950ebfe3456fc0d42f8d058a5d2b3979 (MD5)

cryptanalysis of some signature schemes with message recovery

IEEE Computer Society

分离扇回旋加速器的接受度及效率；Acceptance and efficiency of sector-separated cyclotron

以9.7MeV/u的238U36+,5.62MeV/u的70Zn10+为典型离子,分析并模拟了分离扇回旋加速器(SSC)的注入、加速和引出,得到了SSC在理论等时场下横向和纵向的接受度。为了研究SSC在实际情况下的接受度,在实测场的基础上采用Kr-Kb方法以及Lagrange插值方法建立了与实际比较符合的等时场,计算了该等时场下SSC横向和纵向的接受度,发现了导致SSC实际接受度和传输效率低的主要原因在于注入系统中的MSI3元件和引出系统中的MSE3元件设计存在缺陷。模拟结果显示,通过改变MSI3和MSE3的曲率或者垫铁改变元件内部的场分布可以改善SSC的实际接受度和传输效率。

message from the workshop chairs the first international workshop on program debugging in china (iwpdc 2010)

National Laboratory for Parallel and Distributed Processing; The University of Hong Kong