114 resultados para Hardware

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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Coordinated measurement of temperature, velocity and free surface oscillation were obtained by using the drop shaft facility for microgravity experiments of half floating zone convection. The ground-based studies gave transition from steady to oscillatory convection for multi-quantities measurement.

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This paper describes a special-purpose neural computing system for face identification. The system architecture and hardware implementation are introduced in detail. An algorithm based on biomimetic pattern recognition has been embedded. For the total 1200 tests for face identification, the false rejection rate is 3.7% and the false acceptance rate is 0.7%.

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Experimental hardware has been developed to perform experiments on the Marangoni migration of drops in the case of intermediate Reynolds numbers in a microgravity environment. The experiments were conducted using the drop shaft free fall facility with a 4.5 second microgravity period in the Microgravity Laboratory of Japan. In this experiment, the thermocapillary velocity of drop migration was measured for drops of different sizes in a series of temperature gradients.

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This short communication presents our recent studies to implement numerical simulations for multi-phase flows on top-ranked supercomputer systems with distributed memory architecture. The numerical model is designed so as to make full use of the capacity of the hardware. Satisfactory scalability in terms of both the parallel speed-up rate and the size of the problem has been obtained on two high rank systems with massively parallel processors, the Earth Simulator (Earth simulator research center, Yokohama Kanagawa, Japan) and the TSUBAME (Tokyo Institute of Technology, Tokyo, Japan) supercomputers.

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A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost close to zero. Compared with previous technique, this is a lensless architecture which minimizes the hardware requirement, and it is used for the encryption of digital image.

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A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost closed to zeros. Compared with previous technique, this is a lensless architecture, which minimizes the hardware requirement. (c) 2006 Elsevier GmbH. All rights reserved.

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(250ps)

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On the basis of DBF nets proposed by Wang Shoujue, the model and properties of DBF neural network were discussed in this paper. When applied in pattern recognition, the algorithm and implement on hardware were presented respectively. We did experiments on recognition of omnidirectionally oriented rigid objects on the same level, using direction basis function neural networks, which acts by the method of covering the high dimensional geometrical distribution of the sample set in the feature space. Many animal and vehicle models (even with rather similar shapes) were recognized omnidirectionally thousands of times. For total 8800 tests, the correct recognition rate is 98.75%, the error rate and the rejection rate are 0.5% and 1.25% respectively. (C) 2003 Elsevier Inc. All rights reserved.

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Based on the introduction of the traditional mathematical models of neurons in general-purpose neurocomputer, a novel all-purpose mathematical model-Double synaptic weight neuron (DSWN) is presented, which can simulate all kinds of neuron architectures, including Radial-Basis-Function (RBF) and Back-propagation (BP) models, etc. At the same time, this new model is realized using hardware and implemented in the new CASSANN-II neurocomputer that can be used to form various types of neural networks with multiple mathematical models of neurons. In this paper, the flexibility of the new model has also been described in constructing neural networks and based on the theory of Biomimetic pattern recognition (BPR) and high-dimensional space covering, a recognition system of omni directionally oriented rigid objects on the horizontal surface and a face recognition system had been implemented on CASSANN-H neurocomputer. The result showed DSWN neural network has great potential in pattern recognition.

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A new model of pattern recognition principles-Biomimetic Pattern Recognition, which is based on "matter cognition" instead of "matter classification", has been proposed. As a important means realizing Biomimetic Pattern Recognition, the mathematical model and analyzing method of ANN get breakthrough: a novel all-purpose mathematical model has been advanced, which can simulate all kinds of neuron architecture, including RBF and BP models. As the same time this model has been realized using hardware; the high-dimension space geometry method, a new means to analyzing ANN, has been researched.

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In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

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The Double Synapse Weighted Neuron (DSWN) is a kind of general-purpose neuron model, which with the ability of configuring Hyper-sausage neuron (HSN). After introducing the design method of hardware DSWN synapse, this paper proposed a DSWN-based specific purpose neural computing device-CASSANN-IIspr. As its application, a rigid body recognition system was developed on CASSANN-IIspr, which achieved better performance than RIBF-SVMs system.

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