基于ARM的可编程控制系统实现

采用ARM设计小型可编程控制器,提供基于以太网和OPC标准的组态监控接口。用户采用符合IEC61131-3标准的梯形图方式对控制器自由编程,并通过计算机网络对其进行程序调试、下载和数据通信,从而实现了一套经济实用的小型可编程控制系统。

新型汽车变速箱压装机控制系统的设计

文章介绍了一种新型汽车变速箱压装机控制系统的设计,对系统的硬件组态及控制功能作了主要描述。汽车变速箱压装机是汽车变速箱装配流水线上的一台机电一体化专用自动装配设备,该机除具有自动压装功能、自动检测报警功能外,还能与装配管理系统联网,实现网络化管理与控制功能。整个系统采用了SLC500可编程控制器、触摸屏、安全光幕控制器等控制部件,为机床提供了安全可靠的装配质量保证。

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Pulse compression by filamentation in argon with an acoustic optical programmable dispersive filter for predispersion compensation

We have experimentally demonstrated pulses 0.4 mJ in duration smaller than 12 fs; with an excellent spatial beam profile by self-guided propagation in argon. The original 52 fs pulses from the chirped pulsed amplification laser system are first precompressed to 32 fs by inserting an acoustic optical programmable dispersive filter instrument into the laser system for spectrum reshaping and dispersion compensation, and the pulse spectrum is subsequently broadened by filamentation in an argon cell. By using chirped mirrors for post-dispersion compensation, the pulses are successfully compressed to smaller than 12 fs.

A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

An adaptive controller for a class of nonlinear system using direction basis function

For a class of nonlinear dynamical systems, the adaptive controllers are investigated using direction basis function (DBF) in this paper. Based on the criterion of Lyapunov' stability, DBF is designed which guarantees that the output of the controlled system asymptotically tracks the reference signals. Finally, the simulation shows the good tracking effectiveness of the adaptive controller.

Quantum well controller

A quantum well controller (QWC) consisting of a direct-gap/indirect-gap quantum well and a doping interface is proposed to control the dynamic operation of the Gunn active layer. Through the Monte Carlo simulation a new relaxation mode for this new device is found. The oscillation and amplification behavior of the Gunn active layer under the control of the QWC is investigated theoretically and experimentally. All work demonstrates the great control capacity of the QWC and provides a new way to improve the performance of semiconductor devices. A new oscillation diode made of the QWC and a Gunn active layer has been designed and fabricated. In the 8 mm band the highest pulse output power of these diodes is 2.55 W and the highest conversion efficiency is 18%.

Packing LUT clusters with network flow programming

This paper describes a two-step packing algorithm for LUT clusters of which the LUT input multipliers are depopulated. In the first step, a greedy algorithm is used to search for BLE locations and cluster inputs. If the greedy algorithm fails, the second step with network flow programming algorithm is employed. Numerical results illustrate that our two-step packing algorithm obtains better packing density than one-step greedy packing algorithm.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

yet another meta-language for programming language processing

The formal specification language LFC was designed to support formal specification acquisition. However, it is yet suited to be used as a meta-language for specifying programming language processing. This paper introduces LFC as a meta-language, and compares it with ASF+SDF, an algebraic specification formalism that can also be used to programming languages.