The gated integration technique for the accurate measurement of the autocorrelation function of speckle intensities scattered from random phase screens

A new approach based on the gated integration technique is proposed for the accurate measurement of the autocorrelation function of speckle intensities scattered from a random phase screen. The Boxcar used for this technique in the acquisition of the speckle intensity data integrates the photoelectric signal during its sampling gate open, and it repeats the sampling by a preset number, in. The average analog of the in samplings output by the Boxcar enhances the signal-to-noise ratio by root m, because the repeated sampling and the average make the useful speckle signals stable, while the randomly varied photoelectric noise is suppressed by 1/ root m. In the experiment, we use an analog-to-digital converter module to synchronize all the actions such as the stepped movement of the phase screen, the repeated sampling, the readout of the averaged output of the Boxcar, etc. The experimental results show that speckle signals are better recovered from contaminated signals, and the autocorrelation function with the secondary maximum is obtained, indicating that the accuracy of the measurement of the autocorrelation function is greatly improved by the gated integration technique. (C) 2006 Elsevier Ltd. All rights reserved.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

宽频带地震数据采集系统的研制

The seismic data acquisition system is the most important equipment for seismic prospecting. The geophysicists have been paying high attention to the specification of the equipment used in seismic prospecting. Its specification and performance are of great concerned to acquire precisely and accurately seismic data, which show us stratum frame. But, by this time, limited by the technology, most of the Broad-band Seismic Recorder (BSR) for lithosphere research of our country were bought from fremdness which were very costliness and maintained discommodiously. So it is very important to study the seismic data acquisition system.The subject of the thesis is the research of the BSR, several items were included, such as: seismic data digitizer and its condition monitor design.In the first chapter, the author explained the significance of the implement of BSR, expatiated the requirement to the device and introduced the actuality of the BSR in our country.In the second chapter, the collectivity architecture of the BSR system was illustrated. Whereafter, the collectivity target and guideline of the performance of the system design were introduced. The difficulty of the system design and some key technology were analyzed, such as the Electro Magnetic Compatibility (EMC), system reliability technology and so on.In the third chapter, some design details of BSR were introduced. In the recorder, the former analog to digital converter (ADC) was separated from the later data transition module. According to the characteristic of seismic data acquisition system, a set high-resolution 24-bit ADC chip was chosen to the recorder design scheme. As the following part, the noise performance of the seismic data channel was analyzed.In the fourth chapter, the embedded software design of each board and the software design of the workstation were introduced. At the same time the communication protocol of the each module was recommendedAt the last part of this thesis, the advantages and the practicability of the BSR system design were summarized, and the next development items were suggested.

多路温度测控系统的设计

目的利用单片机技术设计多路温度测控系统,实现多路温度的测量和控制.方法系统以单片机AT89C52为核心,利用多路转换器和新型数字器件MAX6675构成8路K型热电偶温度测量电路,利用D/A转换器AD7528和驱动电路构成输出电路,实现8路一一对应的闭环温度测量控制.系统软件采用PID控制器.结果实践证明,可根据需要增减系统温度信号采样通道的数目,使用软件抗干扰措施,提高了采样数据的可靠性.简化了输入输出硬件结构,使系统具有低成本高速度和较好的测量控制精度.结论多路温度测控系统作为整机适用于现场测量控制应用,也可作为多路温度控制模块应用在体积小、温度测量精度要求较高的大型系统中.

A Dynamic Model For Ice-Induced Vibration Of Structures

A dynamic model for the ice-induced vibration (IIV) of structures is developed in the present study. Ice properties have been taken into account, such as the discrete failure, the dependence of the crushing strength on the ice velocity, and the randomness of ice failure. The most important prediction of the model is to capture the resonant frequency lock-in, which is analog to that in the vortex-induced vibration. Based on the model, the mechanism of resonant IIV is discussed. It is found that the dependence of the ice crushing strength on the ice velocity plays an important role in the resonant frequency lock-in of IIV. In addition, an intermittent stochastic resonant vibration is simulated from the model. These predictions are supported by the laboratory and field observations reported. The present model is more productive than the previous models of IIV.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

Fabrication of a novel silica PLC hybrid integrated triplexer

A new-style silica planar lightwave circuit (PLC) hybrid integrated triplexer, which can demultiplex 1490-nm download data and 1550-nm download analog signals, as well as transmit 1310-nm upload data, is presented. It combines SiO2 arrayed waveguide gratings (AWGs) with integrated photodetectors (PDs) and a high performance laser diode (LD). The SiO2 AWGs realize the three-wavelength coarse wavelength-division multiplexing (CWDM). The crosstalk is less than 40 dB between the 1490- and 1550-nm channels, and less than 45 dB between 1310- and 1490- or 1550-nm channels. For the static performances of the integrated triplexer, its upload output power is 0.4 mW, and the download output photo-generated current is 76 A. In the small-signal measurement, the upstream 3-dB bandwidth of the triplexer is 4 GHz, while the downstream 3-dB bandwidths of both the analog and digital sections reach 1.9 GHz.

甘肃西峰黄土剖面500 ka以来的蜗牛化石记录及其古气候、古环境变化研究

The loess-paleosol sequences in China are among the best continental records of paleoclimate changes. Although numerous sedimentological and geochemical studies have contributed greatly to the understanding of past climate changes during this period, it is still necessary to decipher more details through investigating these sequences using various approaches including biological analyses. In this study, we analyze the mollusk fossil assemblages preserved in the upper part of the Xifeng section, from the fifth loess layer (L5) to the Holocene soil (S0), with the sampling interval of 10 cm. The main results and conclusions obtained are as follows: 1. A continuous terrestrial mollusk fossil record, covering the past 500 ka, has been obtained from the Xifeng loess-paleosol sequence, which provides important biological data for the study of paleoenvironmental changes in the Loess Plateau and its comparison with marine record during this period. A total of 475 mollusk assemblages were studied, and twenty-one species have been identified among the 210,000 mollusk individuals counted. Among these species, most have modern representatives and are found in previous terrestrial mollusk studies of Chinese loess-paleosol sequences. Thus, they can be grouped into cold-aridiphilous, thermo-humidiphilous, oriental, and cool-humidiphilous ecological groups, as defined by previous studies. 2. Comparison of mollusk assemblages between the last five glacials and four interglacials and Holocene shows very different climate conditions. The warmest period occurred at MIS 11, MIS 5e, and Holocene, respectively. The coldest period is the Last Glacial Maximam, rather than the MIS 12. 3. Our mollusk record provides insight into the climate conditions in the Loess Plateau during the MIS 11, interpreted as the closest analog to the present interglacial. S4 paleosol, equivalent of MIS 11, developed under two major different climate regimes: ranging from the very warm–humid early phase to the mild-cool late interval. Furthermore, a cooling spell has been documented at the interglacial optimum, reflecting unstable climate conditions. The early warm–humid conditions lasted over 30 ka, supporting that MIS 11 is a unique long interglacial in the Quaternary climate history. 4. Comparison of MIS 11 and Holocene climates based on the mollusk species compositions indicates major differences. The climate at the early part of MIS 11 was warmer and more humid than during the Holocene optimum period, but the conditions during the late part of MIS 11 were similar to or cooler than late Holocene. Our study indicates that the extent of warming during the Holocene might be significantly less than the conditions that prevailed during the early part of MIS 11 interglacial period. 5. Two strong summer monsoon events were observed during the MIS 12 and MIS 10. They correspond to the maximam values of insolation gradient between low and high latitudes, suggesting a causal linkage. 6. Our study, combined with the previously investigated Luochuan land snail record, reveals that the climate in the Loess Plateau during MIS 3 experienced three stages: relatively warm, humid climate prevailed during MIS 3c, relatively cold, dry climate during MIS 3b, and relatively warm-humid period during MIS 3a. Climate at this time fluctuated frequently in Luochuan, and changed from warm-cool to cold-dry in Xifeng. Our results reveal that the relatively warm-humid climate during MIS 3c may be resulted from an increasing insolation gradient controlled by obliquity. Our result also reveals that obvious regional difference existed in the Loess Plateau during MIS 3. A greater climate gradient occurred during this time compared with today’s climate pattern in the Loess Plateau.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

An analysis of the performance of a new high-speed single-way analog switch

This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.

Cascaded Fresnel digital hologram and its application to watermarking

A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost close to zero. Compared with previous technique, this is a lensless architecture which minimizes the hardware requirement, and it is used for the encryption of digital image.

Digital holographic interferometry and the angular spectrum method applied to measuring the domain inversion in ferroelectric crystal

The application of digital holographic interferometry on the quantitative measurement of the domain inversion in a RuO2: LiNbO3 crystal wafer is presented. The recorded holograms are reconstructed by the angular spectrum method. From the reconstructed phase distribution we can clearly observe the boundary between the inverted and un-inverted domain regions. Comparisons with the results reconstructed by use of the Fresnel transform method are given. Factors that influence the measurement include the spectrum filter size and the spectrum movement are discussed. The spectrum filter size has an effect on the measurement of the details. Although the spectrum movement affects every single reconstructed image, it has no influence on the final measurement.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.