201 resultados para ambipolar transistors


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This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

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A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

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Improved electrical properties of AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures grown by metalorganic chemical vapor deposition (MOCVD) were achieved through increasing the Al mole fraction in the AlGaN barrier layers. An average sheet resistance of 326.6 Omega/sq and a good resistance uniformity of 98% were obtained for a 2-inch Al0.38Ga0 62N/GaN HEMT structure. The surface morphology of AlxGa1-xN/GaN HEMT structures strongly correlates with the Al content. More defects were formed with increasing Al content due to the increase of tensile strain, which limits further reduction of the sheet resistance. (c) 2006 WILEY-VCH Verlag GmbH & Co KGaA, Weinheim.

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The mobility of channel electron, for partially depleted Sol nMOSFET in this paper, decreases with the increase of implanted fluorine dose in buried oxide layer. But, the experimental results also show that it is larger for the transistor corresponding to the lowest implantation dose than no implanted fluorine in buried layer. It is explained in tern-is of a "lubricant" model. Mien fluorine atoms are implanted in the top silicon layer, the mobility is the largest. In addition, a positive shift of threshold voltage has also been observed for the transistors fabricated on the Sol wafers processed by the implantation of fluorine. The causes of all the above results are discussed.

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The valence band offset (VBO) of MgO/TiO2 (rutile) heterojunction has been directly measured by Xray photoelectron spectroscopy. The VBO of the heterojunction is determined to be 1.6 +/- 0.3 eV and the conduction band offset (CBO) is deduced to be 3.2 +/- 0.3 eV, indicating that the heterojunction exhibits a type-I band alignment. These large values are sufficient for MgO to act as tunneling barriers in TiO2 based devices. The accurate determination of the valence and conduction band offsets is important for use of MgO as a buffer layer in TiO2 based field-effect transistors and dye-sensitized solar cells.

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The influences of channel layer width, spacer layer width, and delta-doping density on the electron density and its distribution in the AlSb/InAs high electron mobility transistors (HEMTs) have been studied based on the self-consistent calculation of the Schrodinger and Poisson equations with both the strain and nonparabolicity effects being taken into account. The results show that, having little influence on the total two dimensional electron gas (2DEG) concentration in the channel, the HEMT's channel layer width has some influence on the electron mobility, with a channel as narrow as 100-130 angstrom being more beneficial. For the AlSb/InAs HEMT with a Te delta-doped layer, the 2DEG concentration as high as 9.1 X 10(12) cm(-2) can be achieved in the channel by enhancing the delta-doping concentration without the occurrence of the parallel conduction. When utilizing a Si delta-doped InAs layer as the electron-supplying layer of the AlSb/InAs HEMT, the effect of the InAs donor layer thickness is studied on the 2DEG concentration. To obtain a higher 2DEG concentration in the channel, it is necessary to use an InAs donor layer as thin as 4 monolayer. To test the validity of our calculation, we have compared our theoretical results (2DEG concentration and its distribution in different sub-bands of the channel) with the experimental ones done by other groups and show that our theoretical calculation is consistent with the experimental results.

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有机薄膜晶体管由于具有低成本、易于柔性基底兼容、可以大面积制作等优点,已经在有源平板显示、低端电子产品以及传感器等方面显示出了极大的应用潜力。由于有机异质结具有一些与无机异质结不同的特性,而基于有机异质结的电子器件也显示出越来越受到人们的关注。因此,本论文的工作主要集中在有机异质结薄膜晶体管的功能与薄膜形貌的研究上。 1. 我们首先研究了BP2T/F16CuPc异质结的特征(第二章)。在BP2T/F16CuPc异质结界面处,BP2T的能级向上弯曲,F16CuPc的能级向下弯曲,费米能级穿越F16CuPc的LUMO。并且在其异质结界面处,存在载流子的累积,其中空穴累积在BP2T中,累积厚度大约为10 nm,电子累积在F16CuPc中,累积厚度大约为20 nm。 2. 我们利用BP2T/F16CuPc异质结的特征,通过改变BP2T的厚度,在BP2T/F16CuPc有机异质结薄膜晶体管中实现了晶体管的三种工作模式(第三章):n沟道、双极型和p沟道。在n沟道模式下,电子迁移率随着厚度的增加而增大;在双极型模式下,电子和空穴的迁移率先随着BP2T厚度增加而增加,当BP2T的厚度超过5 nm 时,电子和空穴的迁移率分别达到最大值,随着BP2T厚度的继续增加,电子和空穴的迁移率就开始下降;在p沟道模式下,空穴的迁移率不在随着BP2T厚度的变化而变化。通过对BP2T薄膜进行原子力表征,我们发现这些规律是与BP2T薄膜的表面形貌密切相关的,并给出了载流子累积的示意图。 3. 根据BP2T/F16CuPc有机异质结薄膜晶体管在三种工作模式中所具有的规律,将其双极型的工作模式推广到金属酞菁体系、菲体系、硫茚体系以及萘体系与F16CuPc的异质结材料对中,并分别从第一半导体的生长方式、 分子长度以及迁移率等方面对实现高性能的双极型传输进行了讨论(第四章);在BP2T/F16CuPc有机异质结薄膜晶体管中将单极型电子的迁移率提高到了0.06 cm2/V•s,将双极型电子的迁移率提高到了0.1 cm2/V•s,并且观察到了F16CuPc在BP2T上具有弱外延生长;在NaT4/F16CuPc有机异质结薄膜晶体管中通过设计新的器件构型,实现了高迁移率、高开关比的p型常开型工作模式。

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有机薄膜晶体管中以并五苯和齐聚唾酚为代表的几种有机半导体材料材料多晶薄膜的迁移率已经达到1cm2V-1s-l以上,已经非常接近这些材料单晶的迁移率,也是目前有机薄膜晶体管所使用的材料中迁移率最高的。但是这几种材料都具有合成困难,价格昂贵、稳定性较差的缺点。金属酞警是一种具有较好热和化学的稳定性、价格便宜、可以在商业上直接购得大量高纯度产品的有机半导体材料。它的单晶迁移率很高,但是现在它多晶薄膜的迁移率比单晶的迁移率低两个量级。因此尽快提高这种金属酞普多晶薄膜的迁移率是目前有机薄膜晶体管研究的一个迫切要求。在对并五苯材料的研究中,认为采用提高有机半导体薄膜的有序性、有机薄膜晶体管中的载流子注入的方法可以提高其多晶薄膜中的迁移率,深入的机理有待更进一步的研究。因此本论文的工作主要集中在以下三个方面:(1)以酞普铜为研究对象,利用经典的薄膜生长理论解释了生长条件对薄膜形态结构的影响。然后在薄膜生一氏理论的指导下,制备出大尺寸,高有序,连续的酞普铜薄膜。在这个基础上获得了基于酞普铜薄膜的有机薄膜晶体管目前最高的迁移率。并且成功的将这种方法扩展到了平面型单酞警、全氟代酞普铜、并五苯等多个有机半导体材料上。〔2〕发明了一种新有机薄膜晶体管构型,夹心型有机薄膜晶体管。通过提高器件中的载流子注入,将基于金属酞普薄膜的有机薄膜晶体管的迁移率提高了一个量级,接近了金属酞瞥单晶中的迁移率,达到了目前平板显示中的大量使用的非晶硅薄膜晶体管的水平。并.目.成功的将这一构型扩展到了更广阔的有机半导体材料上。〔3〕利用两种单金属酞背共晶复合得到了比单一组分具有更高迁移率的酞普共晶复合材料的同时,发明了一种利用两种有机半导体材料复合来获得高迁移率有机半导体材料的物理方法。利用多种表征手段对单金属酞蓄共晶材料进行了表征,寻找到了单金属酞普共晶复合材料高迁移率的原因。

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有机薄膜晶体管由于具有操作温度低、可以大面积加工和兼容柔性基底等优点,在有源矩阵显示、集成电路和化学传感器等方面显示出广泛的应用潜力。基于这个原因,有关有机半导体材料和器件的研究已经成为当前的热点。从实际应用的角度考虑,当前有机薄膜晶体管的器件性能和单一的工作模式还不能充分的满足实际的需要。因此如何提高有机薄膜晶体管的器件性能、开发多工作模式的器件成为有机电子学领域研究人员的重要挑战。本论文的工作以有机薄膜晶体管器件为主要研究对象。在对二种栅绝缘层的有机薄膜晶体管的研究基础上,提出了有机/无机双介电层有机薄膜晶体管的概念,解决器件的闭值电压和栅源漏电的问题;通过的对有机薄膜晶体管中电荷注入的研究的基础上,提出了含有缓冲层的有机薄膜晶体管,显著的改善了电荷注入效率,提高了器件性能。在对异质结型器件研究的基础上,获得了耗尽型和双极型有机薄膜晶体管,满足实际应用对多种工作模式有机薄膜晶体管的需求。论文的主体工作主要分为基于不同栅绝缘层的有机薄膜晶体管的研究,有机薄膜晶体管中接触效应的研究以及异质结型有机晶体管三个部分其具体内容如下:(l)基于不同栅绝缘层有机薄膜晶体管的研究。通过对有机晶体管中常用的高介电和低介电绝缘层对器件性能的影响进行了系统的研究,在有机晶体管构建中提出了有机/无机双介电层的概念。这一概念包含两个方面意义:一方面采用的双绝缘层分别为一层有机材料和一层无机材料的双介电层;另一方面无机介电层使用的是高介电常数的材料,有机部分为低介电常数材料。有机半导体沉积在这种方法构建的栅绝缘层基底上,改善了有机半导体的薄膜形态,提高了有机半导体层和无机基底的乳附力,从而达到了优化了器件电子性质的目的。与此同时解决了在当前含有高介电绝缘栅的有机晶体管中存在的高漏电的问题。通过这种方法构建的有机薄膜晶体管具有低阂值电压、低漏电、高迁移率等优点。由于我们在有机绝缘层的加工中采用了化学修饰的方法,该方法有加工简便、性质稳定好所以具有很好的实际应用前景。(2)有机薄膜晶体管中接触效应的研究。通过实验中采用TML(Transfer-Line一Method)的方法系统的研究了酞著铜薄膜晶体管中的接触效应,首次获得了酞著铜和金电极接触电阻定量化的结果。通过改变不同的电极材料,研究了不同的源漏电极对有机晶体管器件性能的影响。在此基础上为了能减小有机晶体管中的接触电阻,改善电荷注入效率,我们采用了在源漏电极和有机半导体之间插入一层高电导率的有机材料的方法,有效的降低了金属和有机半导体的注入势垒,增大了电荷隧穿几率,从而显著的改善了有机晶体管的器件性质。(3)异质结型有机晶体管。为了推动有机晶体管在集成互补电路中的应用,多工作模式的有机晶体管是需要的。在这里,我们把有机的异质结引入到有机晶体管的制备中,分别获得了高性能的耗尽型和双极型有机晶体管。通过了一系列的设计实验,我们提出了双沟道的载流子输运模型,为异质结型晶体管中双载流子的输运机制提供了理论上的解释。此外,我们通过有机异质结厚度的调节,进而改变沟道区的载流子密度,从而可以有效的调节了器件的阂值电压。当前的研究结果的意义在于利用的有机的异质结效应可以获得不同阂值电压的全塑型有机晶体管,为其实际中的广泛应用开辟了道路。此外我们还在同一基底上构建了基于一个常开型(耗尽)和一个常关型(累积)两个有机晶体管的反向器电路,从而表明异质结型有机晶体管在集成电路方面具有广泛的应用潜力。综上所述,本论文对目前有机薄膜晶体管器件中存在的问题进行了深入的研究。在此基础上,针对不同的问题分别提出了三种功能性的有机晶体管,优化了器件的性能。当前的研究也将为加速有机薄膜晶体管的在实际中的应用做出贡献。

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We report on high magnetic fields (up to 40 T) cyclotron resonance, quantum Hall effect and Shubnikov-de-Hass measurements in high frequency transistors based on Si-doped GaN-AlGaN heterojunctions. A simple way of precise modelling of the cyclotron absorption in these heterojunctions is presented, We clearly establish two-dimensional electrons to be the dominant conducting carriers and determine precisely their in-plane effective mass to be 0.230 +/- 0.005 of the free electron effective mass. The increase of the effective mass with an increase of two-dimensional carrier density is observed and explained by the nonparabolicity effect. (C) 1997 American Institute of Physics.

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The influence of annealed ohmic contact metals on the electron mobility of a two dimensional electron gas (2DEG) is investigated on ungated AlGaN/GaN heterostructures and AlGaN/GaN heterostructure field effect transistors (AlGaN/GaN HFETs). Current-voltage (I-V) characteristics for ungated AlGaN/GaN heterostructures and capacitance-voltage (C-V) characteristics for AlGaN/GaN HFETs are obtained, and the electron mobility for the ungated AlGaN/GaN heterostructure is calculated. It is found that the electron mobility of the 2DEG for the ungated AlGaN/GaN heterostructure is decreased by more than 50% compared with the electron mobility of Hall measurements. We propose that defects are introduced into the AlGaN barrier layer and the strain of the AlGaN barrier layer is changed during the annealing process of the source and drain, causing the decrease in the electron mobility.

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This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator (SO1) technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic "1" while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable "read" operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin (SNM) of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

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A power amplifier MIC with power combining based on AlGaN/GaN HEMTs was fabricated and measured. The amplifier consists of four 10×120μm transistors. A Wilkinson splitters and combining were used to divide and combine the power. By biasing the amplifier at V_(DS) =40V, I(DS)= 0. 9A, a maximum CW output power of 41. 4dBm with a maximum power added efficiency (PAE) of 32. 54% and a power combine efficiency of 69% was achieved at 5. 4GHz.

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A technology for the monolithic integration of resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs) is developed. Molecular beam epitaxy is used to grow an RTD on a HEMT structure on GaAs substrate. The RTD has a room temperature peak-to-valley ratio of 5.2:1 with a peak current density of 22.5kA/cm~2. The HEMT has a 1μm gate length with a-1V threshold voltage. A logic circuit called a monostableto-bistable transition logic element (MOBILE) circuit is developed. The experimental result confirms that the fabricated logic circuit operates successfully with frequency operations of up to 2GHz.

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A monolithic integrated CMOS preamplifier is presented for neural recording applications. Two AC-coupied capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface. Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier. A novel analysis is given to determine the noise power spectral density. Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVmax, integrated from 0. 1Hz to 1kHz. The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.