75 resultados para Induction (Logic)


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The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

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The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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Submitted by 张磊 (zhanglei@semi.ac.cn) on 2010-06-03T13:47:18Z No. of bitstreams: 1 Directed XOR_XNOR.pdf: 556366 bytes, checksum: c67167a8648c1242c1eec35d6cca24f6 (MD5)

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The need to make default assumptions is frequently encountered in reasoning about incompletely specified worlds. Inferences sanctioned by default are best viewed as beliefs which may well be modified or rejected by subsequent observations. It is this property which leads to the non-monotonicity of any logic of defaults. In this paper we propose a logic for default reasoning. We then specialize our treatment to a very large class of commonly occuring defaults. For this class we develop a complete proof theory and show how to interface it with a top down resolution theorem prover. Finally, we provide criteria under which the revision of derived beliefs must be effected.

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A technique is presented for ascertaining when a (finite-state) partial process specification is adequate, in the sense of being specified enough, for contexts in which it is to be used. The method relies on the automatic generation of a modal formula from the partial specification; if the remainder of the network satisfies this formula, then any process that meets the specification is guaranteed to ensure correct behavior of the overall system. Using the results, the authors develop compositional proof rules for establishing the correctness of networks of parallel processes and illustrate their use with several examples