Characterization of the sleep architecture in two species of fruit bat

Bats (Chiroptera) are the second-most abundant mammalian order in the world, occupying a diverse range of habitats and exhibiting many different life history traits. In order to contribute to this highly underrepresented group we describe the sleep architecture of two species of frugivorous bat, the greater short-nosed fruit bat (Cynopterus sphinx) and the lesser dawn fruit bat (Eonycteris spelaea). Electroencephalogram (EEG) and electromyogram (EMG) data were recorded from multiple individuals (>= 5) by telemetry over a 72-h period in a laboratory setting with light/dark cycles equivalent to those found in the wild. Our results show that over a 24-h period both species spent more time asleep than awake (mean 15 h), less than previous reported for Chiroptera (20 h). C sphinx spent significantly more of its non-rapid eye movement sleep (NREM) and rapid eye movement sleep (REM) quotas during the light phase, while E. spelaea divided its sleep-wake architecture equally between both light and dark phases. Comparing the sleep patterns of the two species found that C. sphinx had significantly fewer NREM and REM episodes than E. spelaea but each episode lasted for a significantly longer period of time. Potential hypotheses to explain the differences in the sleep architecture of C. sphinx with E. spelaea, including risk of predation and social interaction are discussed. (C) 2010 Published by Elsevier B.V.

Effect of plant architecture on the structure of epiphytic macro invertebrate communities in a Chinese lake

We examined the effect of different plant architecture types on epiphytic macroinvertebrates of a shallow macrophyte-dominated lake in China. Macroinvertebrates were sampled from four dominant submersed macrophytes in the lake - two dissected plants (Myriophyllum spicatum L. and Ceratophyllum demersum L.) and two undissected plants (Potamogeton maackianus A. Benn. and Vallisneria spiralis L.). Macro invertebrate richness showed significant differences among four submersed macrophyte habitats, and higher density per g of dry plant were associated with dissected plants than undissected plants. The average abundance in dissected plants was as three-six times as in undissected plants. The biodiversity of epiphytic macroinvertebrates was higher in dissected plants than undissected plants. Our results suggest that dissected plants provide different habitat for macroinvertebrates than dissected plant, and this concurs with the hypothesis that the former could support more epiphytic macroinvertebrates than the latter.

A new development on ANN in China - Biomimetic pattern recognition and multi weight vector neurons

A new model of pattern recognition principles-Biomimetic Pattern Recognition, which is based on "matter cognition" instead of "matter classification", has been proposed. As a important means realizing Biomimetic Pattern Recognition, the mathematical model and analyzing method of ANN get breakthrough: a novel all-purpose mathematical model has been advanced, which can simulate all kinds of neuron architecture, including RBF and BP models. As the same time this model has been realized using hardware; the high-dimension space geometry method, a new means to analyzing ANN, has been researched.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.