Watermarks encrypted in the cascaded Fresnel digital hologram

A cascaded Fresnel digital hologram (CFDH) is proposed, together with its mathematical derivation. Its application to watermarking has been demonstrated by a simulation procedure, in which the watermark image to be hidden is encoded into the phase of the host image. The watermark image can be deciphered by the CFDH setup, the reconstructed image shows good quality and the error is almost closed to zeros. Compared with previous technique, this is a lensless architecture, which minimizes the hardware requirement. (c) 2006 Elsevier GmbH. All rights reserved.

Phase-shifting apodizer for next-generation digital versatile disk

The next generation digital versatile disk (DVD) using blue lasers will have a capacity of 13 to 15 Gbytes. Compared with current DVD, the wavelength will be shorter and the numerical aperture (NA) will be higher. But with the increase of NA and decrease of wave length, the depth of focus (DOF) decrease rapidly, which makes it hard for the servo-system to track. We propose an optimized three-portion phase-shifting apodizer to increase the depth of focus and at the same time minimize the spot size, which makes the DOF of next generation DVD comparable to current DVD. The simulation result shows that an optical system with this apodizer also has a good defocus characteristic. (C) 2001 Society of Photo-Optical Instrumentation Engineers.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.