First principles interatomic potential for tungsten based on Gaussian process regression

An accurate description of atomic interactions, such as that provided by first principles quantum mechanics, is fundamental to realistic prediction of the properties that govern plasticity, fracture or crack propagation in metals. However, the computational complexity associated with modern schemes explicitly based on quantum mechanics limits their applications to systems of a few hundreds of atoms at most. This thesis investigates the application of the Gaussian Approximation Potential (GAP) scheme to atomistic modelling of tungsten - a bcc transition metal which exhibits a brittle-to-ductile transition and whose plasticity behaviour is controlled by the properties of $\frac{1}{2} \langle 111 \rangle$ screw dislocations. We apply Gaussian process regression to interpolate the quantum-mechanical (QM) potential energy surface from a set of points in atomic configuration space. Our training data is based on QM information that is computed directly using density functional theory (DFT). To perform the fitting, we represent atomic environments using a set of rotationally, permutationally and reflection invariant parameters which act as the independent variables in our equations of non-parametric, non-linear regression. We develop a protocol for generating GAP models capable of describing lattice defects in metals by building a series of interatomic potentials for tungsten. We then demonstrate that a GAP potential based on a Smooth Overlap of Atomic Positions (SOAP) covariance function provides a description of the $\frac{1}{2} \langle 111 \rangle$ screw dislocation that is in agreement with the DFT model. We use this potential to simulate the mobility of $\frac{1}{2} \langle 111 \rangle$ screw dislocations by computing the Peierls barrier and model dislocation-vacancy interactions to QM accuracy in a system containing more than 100,000 atoms.

Accuracy and transferability of GAP models for tungsten

We introduce interatomic potentials for tungsten in the bcc crystal phase and its defects within the Gaussian Approximation Potential (GAP) framework, fitted to a database of first principles density functional theory (DFT) calculations. We investigate the performance of a sequence of models based on databases of increasing coverage in configuration space and showcase our strategy of choosing representative small unit cells to train models that predict properties only observable using thousands of atoms. The most comprehensive model is then used to calculate properties of the screw dislocation, including its structure, the Peierls barrier and the energetics of the vacancy-dislocation interaction. All software and raw data are available at www.libatoms.org.

Stainless steel sandwich

The Cambridge University's Gordon Laboratory, in collaboration with Fibertech and the Defence Science and Technology Laboratory in the UK, has developed a novel melt spun fiber bore called 'Fibrecore', fabricated entirely from stainless steel with thin faceplates. Fibrecore is typically manufactured by 5mm-long and 70μm thick stainless steel fibers, produced by a melt overflow process. Its entirely metallic construction allows spot welding and tungsten inert gas welding without difficulty. Fibrecore exhibits different energy absorption mechanisms such as core cushioning, core-faceplate delamination, and plastic faceplate deformation, often in a concertina-like fashion. Its low-cost, high structural efficiency and good energy absorption characteristics make it attractive for a range of commercial and military applications. Such applications being evaluated include vehicle body panels, exhaust system noise reduction, low cost filters, and lightweight physical protection. In addition to these characteristics, Fibrecore exhibits properties such as corrosion protection, vibrational damping, and thermal insulation, which also extend its applications.

Microfabrication and application of reservoir pins for liquid transfer in biotechnology

Microarraying involves laying down genetic elements onto a solid substrate for DNA analysis on a massively parallel scale. Microarrays are prepared using a pin-based robotic platform to transfer liquid samples from microtitre plates to an array pattern of dots of different liquids on the surface of glass slides where they dry to form spots diameter < 200 μm. This paper presents the design, materials selection, micromachining technology and performance of reservoir pins for microarraying. A conical pin is produced by (i) conventional machining of stainless steel or wet etching of tungsten wire, followed by (ii) micromachining with a focused laser to produce a microreservoir and a capillary channel structure leading from the tip. The pin has a flat end diameter < 100 μm from which a 500 μm long capillary channel < 15 μm wide leads up the pin to a reservoir. Scanning electron micrographs of the metal surface show roughness on the scale of 10 μm, but the pins nevertheless give consistent and reproducible spotting performance. The pin capacity is 80 nanolitres of fluid containing DNA, and at least 50 spots can be printed before replenishing the reservoir. A typical robot holds can hold up to 64 pins. This paper discusses the fabrication technology, the performance and spotting uniformity for reservoir pins, the possible limits to miniaturization of pins using this approach, and the future prospects for contact and non-contact arraying technology.

Post-CMOS wafer level growth of carbon nanotubes for low-cost microsensors--a proof of concept.

Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

On-chip deposition of carbon nanotubes using CMOS microhotplates.

The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

A high temperature SOI CMOS NO2 sensor

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors. © 2011 American Institute of Physics.