Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Analytical techniques for indentation of viscoelastic materials

Indentation of linearly viscoelastic materials is explored using elastic-viscoelastic correspondence analysis for both conical-pyramidal and spherical indentation. Boltzmann hereditary integrals are used to generate displacement-time solutions for loading at constant rate and creep following ramp loading. Experimental data for triangle- and trapezoidal-loading are examined for commercially-available polymers and compared with analytical solutions. Emphasis is given to the use of multiple experiments to test the fidelity and predictive capability of the obtained material creep function. Plastic deformation occurs in sharp indentation of glassy polymers and is found to complicate the viscoelastic analysis. A new method is proposed for estimating a material time-constant from peak displacement or hardness data obtained in pyramidal indentation tests performed at different loading rates.