TECHNIQUES FOR PRODUCING DEFECT-FREE SOI BY DUAL ELECTRON BEAM HEATING OF DEPOSITED POLYSILICON.

Advances in the dual electron-beam recrystallization technique arising from the fast scanning of a line beam parallel to the edges of narrow seeding windows are described. The resultant recrystallized layers are essentially defect-free, have good surface flatness, and cover large areas.

Thermal characterization of SOI CMOS micro hot-plate gas sensors

This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

Design and optimization of a 250nm SOI LDMOSFET

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

3D thermo-electro-mechanical simulations of gas sensors based on SOI membranes

3D thermo-electro-mechanical device simulations are presented of a novel fully CMOS-compatible MOSFET gas sensor operating in a SOI membrane. A comprehensive stress analysis of a Si-SiO2-based multilayer membrane has been performed to ensure a high degree of mechanical reliability at a high operating temperature (e.g. up to 400°C). Moreover, optimisation of the layout dimensions of the SOI membrane, in particular the aspect ratio between the membrane length and membrane thickness, has been carried out to find the best trade-off between minimal device power consumption and acceptable mechanical stress.

Design and coupled-effect simulations of CMOS micro gas-sensors built on SOI thin membranes

This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro-thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

Design and simulations of SOI CMOS micro-hotplate gas sensors

This paper describes a new generation of integrated solid-state gas-sensors embedded in SOI micro-hotplates. The micro-hotplates lie on a SOI membrane and consist of MOSFET heaters that elevate the operating temperature, through self-heating, of a gas sensitive material. These sensors are fully compatible with SOI CMOS or BiCMOS technologies, offer ultra-low power consumption (under 100 mW), high sensitivity, low noise, low unit cost, reproducibility and reliability through the use of on-chip integration. In addition, the new integrated sensors offer a nearly uniform temperature distribution over the active area at its operating temperatures at up to about 300-350°C. This makes SOI-based gas-sensing devices particularly attractive for use in handheld battery-operated gas monitors. This paper reports on the design of a chemo-resistive gas sensor and proposes for the first time an intelligent SOI membrane microcalorimeter using active micro-FET heaters and temperature sensors. A comprehensive set of numerical and analogue simulations is also presented including complex 2D and 3D electro-thermal numerical analyses. © 2001 Elsevier Science B.V. All rights reserved.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

Low-temperature (≤600 °C) semi-insulating oxygen-doped silicon films by the PECVD technique for large-area power applications

This work describes the deposition, annealing and characterisation of semi-insulating oxygen-doped silicon films at temperatures compatible with polysilicon circuitry on glass. The semi-insulating layers are deposited by the plasma enhanced chemical vapour deposition technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures at a temperature of 350 °C. The as-deposited films are then furnace annealed at 600 °C which is the maximum process temperature. Raman analysis shows the as-deposited and annealed films to be completely amorphous. The most important deposition variable is the N2O SiH4 gas ratio. By varying the N2O SiH4 ratio the conductivity of the annealed films can be accurately controlled, for the first time, down to a minimum of ≈10-7Ω-1cm-1 where they exhibit a T -1 4 temperature dependence indicative of a hopping conduction mechanism. Helium dilution of the reactant gases is shown to improve both film uniformity and reproducibility. A model for the microstructure of these semi-insulating amorphous oxygen-doped silicon films is proposed to explain the observed physical and electrical properties. © 1995.

Low temperature (≤ 600°C) semi-insulating oxygen-doped silicon films by the PECVD technique for large area power applications

This work describes the annealing and characterisation of semi-insulating oxygen-doped silicon films deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The maximum process temperature is chosen to be compatible with large area polycrystalline silicon (poly-Si) circuitry on glass. The most important deposition variable is shown to be the N2O SiH4 gas ratio. Helium dilution results in improved film uniformity and reproducibility. Raman analysis shows the 'as-deposited' and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties. © 1995.

Low loss HF band SOI wine glass bulk mode capacitive square-plate resonator

This paper reports on the design and electrical characterization of a single crystal silicon micromechanical square-plate resonator. The microresonator has been excited in the anti-symmetrical wine glass mode at a resonant frequency of 5.166 MHz and exhibits an impressive quality factor (Q) of 3.7 × 106 at a pressure of 33 mtorr. The device has been fabricated in a commercial foundry process. An associated motional resistance of approximately 50 kΩ using a dc bias voltage of 60 V is measured for a transduction gap of 2 νm due to the ultra-high Q of the resonator. This result corresponds to a frequency-Q product of 1.9 × 1013, the highest reported for a fundamental mode single-crystal silicon resonator and on par with some of the best quartz crystal resonators. The results are indicative of the superior performance of silicon as a mechanical material, and show that the wine glass resonant mode is beneficial for achieving high quality factors allowed by the material limit. © 2009 IOP Publishing Ltd.