Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Seismic performance of geomembrane placed on a slope in a MSW landfill cell -A centrifuge study

Geomembranes are one of the most commonly used geosynthetics in landfill liner systems. They retain the leachate produced by the waste and prevent leakage. Geomembranes may experience harsh environmental conditions such as extreme temperatures or earthquake loading. Earthquake loading can be an extreme loading case for landfills located in seismic regions. This study, based on dynamic centrifuge testing, investigates the effects of simulated earthquake loading on the tension experienced bythe geomembrane on a landfill slope. The landfill modeled in the dynamic centrifuge test was a municipal solid waste (MSW) landfill cell with a single geomembrane-clay liner system (45° side slope and 10 m slope length). The paper shows that moderate earthquake loading (base acceleration between 0.1g to 0.2g) can result in transient increases of around 20% in geomembrane tension, with permanent tension increases of around 5%.

Influence of ground anchors on topographic amplification at slope crests

One feature of earthquake loading in regions containing sloping ground is a marked increase in accelerations at the crests of slopes. Many field cases exist where such increased accelerations were measured. The observed increase in the amount and severity of observed building damage near the edge of cliff-type topographies has been attributed to the topographic amplification. To counter this, it has been shown that anchoring the soil mass responsible for this to the rest of the stable soil mass can reduce the amount of topographic amplification. In this study, dynamic centrifuge modelling will be used to identify the region affected by topographic amplification in a model slope. The soil accelerations recorded will be compared to those measured in a comparable model treated by anchors. In addition, the tension measured in the anchors will be examined in order to better understand how the anchors are transferring the loads and mitigating these amplifications. © 2010 Taylor & Francis Group, London.

IGBT converters conducted EMI analysis by controlled multiple-slope switching waveform approximation

IGBTs realise high-performance power converters. Unfortunately, with fast switching of the IGBT-free wheel diode chopper cell, such circuits are intrinsic sources of high-level EMI. Therefore, costly EMI filters or shielding are normally needed on the load and supply side. In order to design these EMI suppression components, designers need to predict the EMI level with reasonable accuracy for a given structure and operating mode. Simplifying the transient IGBT switching current and voltage into a multiple slope switching waveform approximation offers a feasible way to estimate conducted EMI with some accuracy. This method is dependent on the availability of high-fidelity measurements. Also, that multiple slope approximation needs careful and time-costly IGBT parameters optimisation process to approach the real switching waveform. In this paper, Active Voltage Control Gate Drive(AVC GD) is employed to shape IGBT switching into several defined slopes. As a result, Conducted EMI prediction by multiple slope switching approximation could be more accurate, less costly but more friendly for implementation. © 2013 IEEE.

High performance nanocomposite thin film transistors with bilayer carbon nanotube-polythiophene active channel by ink-jet printing

Nanocomposite thin film transistors (TFTs) based on nonpercolating networks of single-walled carbon nanotubes (CNTs) and polythiophene semiconductor [poly [5, 5′ -bis(3-dodecyl-2-thienyl)- 2, 2′ -bithiophene] (PQT-12)] thin film hosts are demonstrated by ink-jet printing. A systematic study on the effect of CNT loading on the transistor performance and channel morphology is conducted. With an appropriate loading of CNTs into the active channel, ink-jet printed composite transistors show an effective hole mobility of 0.23 cm 2 V-1 s-1, which is an enhancement of more than a factor of 7 over ink-jet printed pristine PQT-12 TFTs. In addition, these devices display reasonable on/off current ratio of 105-10 6, low off currents of the order of 10 pA, and a sharp subthreshold slope (<0.8 V dec-1). The work presented here furthers our understanding of the interaction between polythiophene polymers and nonpercolating CNTs, where the CNT density in the bilayer structure substantially influences the morphology and transistor performance of polythiophene. Therefore, optimized loading of ink-jet printed CNTs is crucial to achieve device performance enhancement. High performance ink-jet printed nanocomposite TFTs can present a promising alternative to organic TFTs in printed electronic applications, including displays, sensors, radio-frequency identification (RFID) tags, and disposable electronics. © 2009 American Institute of Physics.

Enhanced 10-Gbit/s link performance for directly Modulated complex-coupled DFB lasers via resonance frequency, damping rate, and chirp

This paper demonstrates the respective roles that combined index- and gain-coupling play in the overall link performance of distributed feedback (DFB) lasers. Their impacts on both static and dynamic properties such as slope efficiency, resonance frequency, damping rate, and chirp are investigated. Simulation results are compared with experimental data with good agreement. Transmission-oriented optimization is then demonstrated based on a targeted specification. The design tradeoffs are revealed, and it is shown that a modest combination of index- and gain-coupling enables optimum transmission at 10 Gbit/s.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.