5 resultados para post-growth economy

em Cambridge University Engineering Department Publications Database


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We report on an inexpensive, facile and industry viable carbon nanofibre catalyst activation process achieved by exposing stainless steel mesh to an electrolyzed metal etchant. The surface evolution of the catalyst islands combines low-rate electroplating and substrate dissolution. The plasma enhanced chemical vapour deposited carbon nanofibres had aspect-ratios > 150 and demonstrated excellent height and crystallographic uniformity with localised coverage. The nanofibres were well-aligned with spacing consistent with the field emission nearest neighbour electrostatic shielding criteria, without the need of any post-growth processing. Nanofibre inclusion significantly reduced the emission threshold field from 4.5 V/μm (native mesh) to 2.5 V/μm and increased the field enhancement factor to approximately 7000. © 2011 Elsevier B.V. All rights reserved.

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Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

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This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

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An alternative method for seeding catalyst nanoparticles for carbon nanotubes and nanowires growth is presented. Ni nanoparticles are formed inside a 450 nm SiO2 film on (100) Si wafers through the implantation of Ni ions at fluences of 7.5×1015 and 1.7×1016 ions.cm-2 and post-annealing treatments at 700, 900 and 1100°C. After exposed to the surface by HF dip etching, the Ni nanoparticles are used as catalyst for the growth of vertically aligned carbon nanotubes by direct current plasma enhanced chemical vapor deposition. © 2007 Materials Research Society.

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This research aims to develop a capabilities-based conceptual framework in order to study the stage-specific innovation problems associated with the dynamic growth process of university spin-outs (hereafter referred to as USOs) in China. Based on the existing literature, pilot cases and five critical cases, this study attempts to explore the interconnections between the entrepreneurial innovation problems and the configuration of innovative capabilities (that acquire, mobilise and re-configure the key resources) throughout the lifecycle of a firm in four growth phases. This paper aims to contribute to the literature in a holistic manner by providing a theoretical discussion of USOs' development through adding evidence from a rapid growth emerging economy. To date, studies that have investigated the development of USOs in China recognised the heterogeneity of USOs in terms of capabilities still remain sparse. Addressing this research gap will be of great interest to entrepreneurs, policy makers and venture investors. © Copyright 2010 Inderscience Enterprises Ltd.