A new Lagrangian-Eulerian shell-fluid coupling algorithm based on level sets

We propose a computational method for the coupled simulation of a compressible flow interacting with a thin-shell structure undergoing large deformations. An Eulerian finite volume formulation is adopted for the fluid and a Lagrangian formulation based on subdivision finite elements is adopted for the shell response. The coupling between the fluid and the solid response is achieved via a novel approach based on level sets. The basic approach furnishes a general algorithm for coupling Lagrangian shell solvers with Cartesian grid based Eulerian fluid solvers. The efficiency and robustness of the proposed approach is demonstrated with a airbag deployment simulation. It bears emphasis that in the proposed approach the solid and the fluid components as well as their coupled interaction are considered in full detail and modeled with an equivalent level of fidelity without any oversimplifying assumptions or bias towards a particular physical aspect of the problem.

Viscous layer meshes from level sets on cartesian meshes

The long term goal of our work is to enable rapid prototyping design optimization to take place on geometries of arbitrary size in a spirit of a real time computer game. In recent papers we have reported the integration of a Level Set based geometry kernel with an octree-based cut-Cartesian mesh generator, RANS flow solver and post-processing all within a single piece of software - and all implemented in parallel with commodity PC clusters as the target. This work has shown that it is possible to eliminate all serial bottlenecks from the CED Process. This paper reports further progress towards our goal; in particular we report on the generation of viscous layer meshes to bridge the body to the flow across the cut-cells. The Level Set formulation, which underpins the geometry representation, is used as a natural mechanism to allow rapid construction of conformal layer meshes. The guiding principle is to construct the mesh which most closely approximates the body but remains solvable. This apparently novel approach is described and examples given.

Using Level Sets as the basis for a scalable, parallel geometry engine and mesh generation system

The background to this review paper is research we have performed over recent years aimed at developing a simulation system capable of handling large scale, real world applications implemented in an end-to-end parallel, scalable manner. The particular focus of this paper is the use of a Level Set solid modeling geometry kernel within this parallel framework to enable automated design optimization without topological restrictions and on geometries of arbitrary complexity. Also described is another interesting application of Level Sets: their use in guiding the export of a body-conformal mesh from our basic cut-Cartesian background octree - mesh - this permits third party flow solvers to be deployed. As a practical demonstrations meshes of guaranteed quality are generated and flow-solved for a B747 in full landing configuration and an automated optimization is performed on a cooled turbine tip geometry. Copyright © 2009 by W.N.Dawes.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Patterning and detailed study of human hNT astrocytes on parylene-C/silicon dioxide substrates to the single cell level.

It is estimated that the adult human brain contains 100 billion neurons with 5-10 times as many astrocytes. Although it has been generally considered that the astrocyte is a simple supportive cell to the neuron, recent research has revealed new functionality of the astrocyte in the form of information transfer to neurons of the brain. In our previous work we developed a protocol to pattern the hNT neuron (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/SiO(2) substrates. In this work, we report how we have managed to pattern hNT astrocytes, on parylene-C/SiO(2) substrates to single cell resolution. This article disseminates the nanofabrication and cell culturing steps necessary for the patterning of such cells. In addition, it reports the necessary strip lengths and strip width dimensions of parylene-C that encourage high degrees of cellular coverage and single cell isolation for this cell type. The significance in patterning the hNT astrocyte on silicon chip is that it will help enable single cell and network studies into the undiscovered functionality of this interesting cell, thus, contributing to closer pathological studies of the human brain.