Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Hierarchical approach to timing verification in CMOS VLSI design

This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.

Angular dependence of domain wall resistivity in artificial magnetic domain structures.

We exploit the ability to precisely control the magnetic domain structure of perpendicularly magnetized Pt/Co/Pt trilayers to fabricate artificial domain wall arrays and study their transport properties. The scaling behavior of this model system confirms the intrinsic domain wall origin of the magnetoresistance, and systematic studies using domains patterned at various angles to the current flow are excellently described by an angular-dependent resistivity tensor containing perpendicular and parallel domain wall resistivities. We find that the latter are fully consistent with Levy-Zhang theory, which allows us to estimate the ratio of minority to majority spin carrier resistivities, rho downward arrow/rho upward arrow approximately 5.5, in good agreement with thin film band structure calculations.

Observation of early to full covering stages of ethylene-based CVD of graphene

Scalable growth is essential for graphene-based applications. Recent development has enabled the achievement of the scalability by use of chemical vapor deposition (CVD) at 1000°C with copper as a catalyst and methane as a precursor gas. Here we report our observation of early stage of graphene growth based on an ethylene-based CVD method, capable of reducing the growth temperature to 770°C for monolayer graphene growth on copper. We track the early stages of slow growth under low ethylene flow rate and observe the graphene domain evolution by varying the temperature and growth time. Temperature-dependence of graphene domain density gives an apparent activation energy of 1.0 eV for nucleation.

Sensor graphs for guaranteed cooperative localization performance

A group of mobile robots can localize cooperatively, using relative position and absolute orientation measurements, fused through an extended Kalman filter (ekf). The topology of the graph of relative measurements is known to affect the steady-state value of the position error covariance matrix. Classes of sensor graphs are identified, for which tight bounds for the trace of the covariance matrix can be obtained based on the algebraic properties of the underlying relative measurement graph. The string and the star graph topologies are considered, and the explicit form of the eigenvalues of error covariance matrix is given. More general sensor graph topologies are considered as combinations of the string and star topologies, when additional edges are added. It is demonstrated how the addition of edges increases the trace of the steady-state value of the position error covariance matrix, and the theoretical predictions are verified through simulation analysis.