CHANGES IN PREDICTED MOS DEVICE CHARACTERISTICS DUE TO THE USE OF TWO DIMENSIONAL SOURCE/DRAIN PROFILES.

Two-dimensional MOS device simulation programs such as MINIMOS left bracket 1 right bracket are limited in their validity due to assumptions made in defining the initial two-dimensional source/drain profiles. The two options available to define source/drain regions both construct a two-dimensional profile from one-dimensional profiles normal to the surface. Inaccuracies in forming these source/drain profiles can be expected to effect predicted device characteristics as channel dimensions of the device are reduced. This paper examines these changes by interfacing numerically similated two dimensional source/drain profiles to MINIMOS and comparing predicted I//D-V//D characteristics with 2-D interfacing, 2-D profiles constructed from interfaced 1-D profiles and MINIMOS self generated profiles. Data obtained for simulations of 3 mu m N and P channel devices are presented.

Drain groups in liquefiable soil

One of the major concerns for engineers in seismically active regions is the prevention of damage caused by earthquake-induced soil liquefaction. Vertical drains can aid dissipation of excess pore pressures both during and after earthquakes. Drain systems are designed using standard design charts based around the concept of a unit cell, assuming each drain is surrounded by more drains. It is unclear how predictable drain performance is outside that unit cell concept, for example, drains at the edge of a group. Centrifuge testing is a logical method of performing controlled experiments to establish the efficacy of vertical drains. Centrifuge testing is used to identify the effect of drains dealing with very different catchment areas. The importance of this is further highlighted by the results of a test where the same drains have been modified so that each should behave as a unit cell. It is shown that drains with large catchment areas perform more poorly than unit cells, and also have a knock-on detrimental effect on other drains. Copyright © 2011, IGI Global.

Ink-jet printing of carbon nanotube thin film transistors

Ink-jet printing is an important process for placing active electronics on plastic substrates. We demonstrate ink-jet printing as a viable method for large area fabrication of carbon nanotube (CNT) thin film transistors (TFTs). We investigate different routes for producing stable CNT solutions ("inks"). These consist of dispersion methods for CNT debundling and the use of different solvents, such as N -methyl-2-pyrrolidone. The resulting printable inks are dispensed by ink-jet onto electrode bearing silicon substrates. The source to drain electrode gap is bridged by percolating networks of CNTs. Despite the presence of metallic CNTs, our devices exhibit field effect behavior, with effective mobility of ∼0.07 cm2 /V s and ON/OFF current ratio of up to 100. This result demonstrates the feasibility of ink-jet printing of nanostructured materials for TFT manufacture. © 2007 American Institute of Physics.

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting. © 2005 American Institute of Physics.

A field effect transistor using highly nitrogen-doped CVD diamond for power device applications

A new idea of power device, which contains highly nitrogen-doped CVD diamond and Schottky contact, is proposed to actualise a power device with diamond. Two-dimensional simulation is conducted using ISE TCAD device simulator. While comparably high current is obtained in a transient simulation as expected, this current does not contribute to the drain-source current because of the symmetry of the device. Using an asymmetric structure or bias conditions, the device has high potential as an electric device for extremely high power, high frequency and high temperature. © 2003 Elsevier Science B.V. All rights reserved.

Direct growth of horizontally aligned carbon nanotubes between electrodes and its application to field-effect transistors

This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

Dynamical behavior of damped driven coupled single electron simple harmonic oscillators

Coherent coupling between a large number of qubits is the goal for scalable approaches to solid state quantum information processing. Prototype systems can be characterized by spectroscopic techniques. Here, we use pulsed-continuous wave microwave spectroscopy to study the behavior of electrons trapped at defects within the gate dielectric of a sol-gel-based high-k silicon MOSFET. Disorder leads to a wide distribution in trap properties, allowing more than 1000 traps to be individually addressed in a single transistor within the accessible frequency domain. Their dynamical behavior is explored by pulsing the microwave excitation over a range of times comparable to the phase coherence time and the lifetime of the electron in the trap. Trap occupancy is limited to a single electron, which can be manipulated by resonant microwave excitation and the resulting change in trap occupancy is detected by the change in the channel current of the transistor. The trap behavior is described by a classical damped driven simple harmonic oscillator model, with the phase coherence, lifetime and coupling strength parameters derived from a continuous wave (CW) measurement only. For pulse times shorter than the phase coherence time, the energy exchange between traps, due to the coupling, strongly modulates the observed drain current change. This effect could be exploited for 2-qubit gate operation. The very large number of resonances observed in this system would allow a complex multi-qubit quantum mechanical circuit to be realized by this mechanism using only a single transistor.

Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

A unified circuit model for the polysilicon thin film transistor

This paper describes a unified approach to modelling the polysilicon thin film transistor (TFT) for the purposes of circuit design. The approach uses accurate methods of predicting the channel conductance and then fitting the resulting data with a polynomial. Two methods are proposed to find the channel conductance: a device model and measurement. The approach is suitable because the TFT does not have a well defined threshold voltage. The polynomial conductance is then integrated generally to find the drain current and channel charge, necessary for a complete circuit model. © 1991 The Japan Society of Applied Physics.