49 resultados para ddc:600
em Cambridge University Engineering Department Publications Database
Resumo:
This work describes the deposition, annealing and characterisation of semi-insulating oxygen-doped silicon films at temperatures compatible with polysilicon circuitry on glass. The semi-insulating layers are deposited by the plasma enhanced chemical vapour deposition technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures at a temperature of 350 °C. The as-deposited films are then furnace annealed at 600 °C which is the maximum process temperature. Raman analysis shows the as-deposited and annealed films to be completely amorphous. The most important deposition variable is the N2O SiH4 gas ratio. By varying the N2O SiH4 ratio the conductivity of the annealed films can be accurately controlled, for the first time, down to a minimum of ≈10-7Ω-1cm-1 where they exhibit a T -1 4 temperature dependence indicative of a hopping conduction mechanism. Helium dilution of the reactant gases is shown to improve both film uniformity and reproducibility. A model for the microstructure of these semi-insulating amorphous oxygen-doped silicon films is proposed to explain the observed physical and electrical properties. © 1995.
Resumo:
Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (D av) for 600V Trench IGBT over-voltage protection is proposed. The mix-mode transient simulation proves the clamping capability of the D av when the IGBT is experiencing over-voltage stress in unclamped inductive switching (UIS) test. The spread of avalanche energy, which prevents hot-spot formation, through the help of the avalanche diode feeding back a large fraction of the avalanche current to a gate resistance (R G) is also explained. © 2011 IEEE.
Resumo:
The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.
Resumo:
Vertically aligned carbon nanotubes were synthesized by plasma enhanced chemical vapor deposition using nickel as a metal catalyst. High resolution transmission electron microscopy analysis of the particle found at the tip of the tubes reveals the presence of a metastable carbide Ni3C. Since the carbide is found to decompose upon annealing at 600 degreesC, we suggest that Ni3C is formed after the growth is stopped due to the rapid cooling of the Ni-C interstitial solid solution. A detailed description of the tip growth mechanism is given, that accounts for the composite structure of the tube walls. The shape and size of the catalytic particle determine the concentration gradient that drives the diffusion of C atoms across and though the metal. (C) 2004 American Institute of Physics.
Resumo:
Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6-10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5-1.8kV was realized at VGS = -5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design. © (2009) Trans Tech Publications, Switzerland.
Resumo:
A comprehensive study of the stress release and structural changes caused by postdeposition thermal annealing of tetrahedral amorphous carbon (ta-C) on Si has been carried out. Complete stress relief occurs at 600-700°C and is accompanied by minimal structural modifications, as indicated by electron energy loss spectroscopy, Raman spectroscopy, and optical gap measurements. Further annealing in vacuum converts sp3 sites to sp2 with a drastic change occurring after 1100°C. The field emitting behavior is substantially retained up to the complete stress relief, confirming that ta-C is a robust emitting material. © 1999 American Institute of Physics.
Resumo:
A full-scale experimental study on the structural performance of load-bearing wall panels made of cold-formed steel frames and boards is presented. Six different types of C-channel stud, a total of 20 panels with one middle stud and 10 panels with two middle studs were tested under vertical compression until failure. For panels, the main variables considered are screw spacing (300 mm, 400 mm, or 600 mm) in the middle stud, board type (oriented strand board - OSB, cement particle board - CPB, or calcium silicate board - CSB), board number (no sheathing, one-side sheathing, or two-side sheathing), and loading type (1, 3, or 4-point loading). The measured load capacity of studs and panels agrees well with analytical prediction. Due to the restraint by rivet connections between stud and track, the effective length factor for the middle stud and the side stud in a frame (unsheathed panel) is reduced to 0.90 and 0.84, respectively. The load carrying capacity of a stud increases significantly whenever one- or two-side sheathing is used, although the latter is significantly more effective. It is also dependent upon the type of board used. Whereas panels with either OSB or CPB boards have nearly identical load carrying capacity, panels with CSB boards are considerably weaker. Screw spacing affects the load carrying capacity of a stud. When the screw spacing on the middle stud in panels with one-side sheathing is reduced from 600 mm to 300 mm, its load carrying capacity increases by 14.5 %, 20.6% and 94.2% for OSB, CPB and CSB, respectively.