Metabolite and transcriptome analysis of Campylobacter jejuni in vitro growth reveals a stationary-phase physiological switch.

Campylobacter jejuni is a prevalent cause of food-borne diarrhoeal illness in humans. Understanding of the physiological and metabolic capabilities of the organism is limited. We report a detailed analysis of the C. jejuni growth cycle in batch culture. Combined transcriptomic, phenotypic and metabolic analysis demonstrates a highly dynamic 'stationary phase', characterized by a peak in motility, numerous gene expression changes and substrate switching, despite transcript changes that indicate a metabolic downshift upon the onset of stationary phase. Video tracking of bacterial motility identifies peak activity during stationary phase. Amino acid analysis of culture supernatants shows a preferential order of amino acid utilization. Proton NMR (1H-NMR) highlights an acetate switch mechanism whereby bacteria change from acetate excretion to acetate uptake, most probably in response to depletion of other substrates. Acetate production requires pta (Cj0688) and ackA (Cj0689), although the acs homologue (Cj1537c) is not required. Insertion mutants in Cj0688 and Cj0689 maintain viability less well during the stationary and decline phases of the growth cycle than wild-type C. jejuni, suggesting that these genes, and the acetate pathway, are important for survival.

Capacitive nanoelectromechanical switch based on suspended carbon nanotube array

We present the fabrication and high frequency characterization of a capacitive nanoelectromechanical system (NEMS) switch using a dense array of horizontally aligned single-wall carbon nanotubes (CNTs). The nanotubes are directly grown onto metal layers with prepatterned catalysts with horizontal alignment in the gas flow direction. Subsequent wetting-induced compaction by isopropanol increases the nanotube density by one order of magnitude. The actuation voltage of 6 V is low for a NEMS device, and corresponds to CNT arrays with an equivalent Young's modulus of 4.5-8.5 GPa, and resistivity of under 0.0077 Ω·cm. The high frequency characterization shows an isolation of -10 dB at 5 GHz. © 2010 American Institute of Physics.

Make or buy decision in the context of manufacturing strategy

This paper describes an approach to structuring the make or buy decision process, basing it firmly in the context of an overall manufacturing strategy. The work has been carried out jointly by the University of Cambridge Manufacturing Engineering Group and Lucas Industries. A review of the current state of ideas surrounding the linked issues of vertical integration and make or buy decisions is presented. Important features of the approach include identification of core manufacturing capabilities, assessment of the role of technology in manufacturing, the development of a cost model to support make or buy decisions and a review of the strategic implications of varying degrees of vertical integration.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Free-Space Interconnect for Optical Switch and Analogue Neural Network

In this paper, the architecture of a vector-matrix multiplier (MVM) is simulated. The optical design can be made compact by the use of GRIN lenses for the optical fan-in. The intended application area was in storage area networks (SANs) but the concept can be applied to a neural network. © 2011 Allerton Press, Inc.