Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

Self-aligned, gated arrays of individual nanotube and nanowire emitters

We demonstrate the production of integrated-gate nanocathodes which have a single carbon nanotube or silicon nanowire/whisker per gate aperture. The fabrication is based on a technologically scalable, self-alignment process in which a single lithographic step is used to define the gate, insulator, and emitter. The nanotube-based gated nanocathode array has a low turn-on voltage of 25 V and a peak current of 5 μA at 46 V, with a gate current of 10 nA (i.e., 99% transparency). These low operating voltage cathodes are potentially useful as electron sources for field emission displays or miniaturizing electron-based instrumentation.

Self-healing of fractured GaAs nanowires.

In-situ deformation experiments were carried out in a transmission electron microscope to investigate the structural response of single crystal GaAs nanowires (NWs) under compression. A repeatable self-healing process was discovered in which a partially fractured GaAs NW restored its original single crystal structure immediately after an external compressive force was removed. Possible mechanisms of the self-healing process are discussed.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Design and simulations of SOI CMOS micro-hotplate gas sensors

This paper describes a new generation of integrated solid-state gas-sensors embedded in SOI micro-hotplates. The micro-hotplates lie on a SOI membrane and consist of MOSFET heaters that elevate the operating temperature, through self-heating, of a gas sensitive material. These sensors are fully compatible with SOI CMOS or BiCMOS technologies, offer ultra-low power consumption (under 100 mW), high sensitivity, low noise, low unit cost, reproducibility and reliability through the use of on-chip integration. In addition, the new integrated sensors offer a nearly uniform temperature distribution over the active area at its operating temperatures at up to about 300-350°C. This makes SOI-based gas-sensing devices particularly attractive for use in handheld battery-operated gas monitors. This paper reports on the design of a chemo-resistive gas sensor and proposes for the first time an intelligent SOI membrane microcalorimeter using active micro-FET heaters and temperature sensors. A comprehensive set of numerical and analogue simulations is also presented including complex 2D and 3D electro-thermal numerical analyses. © 2001 Elsevier Science B.V. All rights reserved.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

High velocity vortex channeling in vicinal YBCO thin films

We report on electrical transport measurements at high current densities on optimally doped YBa 2Cu 3O 7-δ thin films grown on vicinal SrTiO 3 substrates. Data were collected by using a pulsed-current technique in a four-probe arrangement, allowing to extend the current-voltage characteristics to high supercritical current densities (up to 24 MA cm -2) and high electric fields (more than 20 V/cm), in the superconducting state at temperatures between 30 and 80 K. The electric measurements were performed on tracks perpendicular to the vicinal step direction, such that the current crossed between ab planes, under magnetic field rotated in the plane defined by the crystallographic c axis and the current density. At magnetic field orientation parallel to the cuprate layers, evidence for the sliding motion along the ab planes (vortex channeling) was found. The signature of vortex channeling appeared to get enhanced with increasing electric field, due to the peculiar depinning features in the kinked vortex range. They give rise to a current-voltage characteristics steeper than in the more off-plane rectilinear vortex orientations, in the electric field range below approximately 1 V/cm. Roughly above this value, the high vortex channeling velocities (up to 8.6 km/s) could be ascribed to the flux flow, although the signature of ohmic transport appeared to be altered by unavoidable macroscopic self-heating and hot-electron-like effects. © 2012 Elsevier B.V. All rights reserved.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.