4 resultados para balanced growth path

em Cambridge University Engineering Department Publications Database


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Lattice-resolved, video-rate environmental transmission electron microscopy shows the formation of a liquid Au-Ge layer on sub-30-nm Au catalyst crystals and the transition of this two-phase Au-Ge/Au coexistence to a completely liquid Au-Ge droplet during isothermal digermane exposure at temperatures far below the bulk Au-Ge eutectic temperature. Upon Ge crystal nucleation and subsequent Ge nanowire growth, the catalyst either recrystallizes or remains liquid, apparently stabilized by the Ge supersaturation. We argue that there is a large energy barrier to nucleate diamond-cubic Ge, but not to nucleate the Au-Ge liquid. As a result, the system follows the more kinetically accessible path, forming a liquid even at 240 degrees C, although there is no liquid along the most thermodynamically favorable path below 360 degrees C.

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This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.