Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Unified analytic model for current-voltage behavior in amorphous oxide semiconductor TFTs

We present a simple and semi-physical analytical description of the current-voltage characteristics of amorphous oxide semiconductor thin-film transistors in the above-threshold and sub-threshold regions. Both regions are described by single unified expression that employs the same set of model parameter values directly extracted from measured terminal characteristics. The model accurately reproduces measured characteristics of amorphous semiconductor thin film transistors in general, yielding a scatter of < 4%. © 1980-2012 IEEE.

Propeller unsteady distortion noise

Turbulence, as naturally occurs in the atmosphere, is known to become highly anisotropic in the presence of the flow induced by a propeller. This turbulent distortion, caused by the streamtube contraction, significantly affects the tonal content of the radiated noise due to turbulence ingestion. We present here an analytic framework in which turbulent distortion may be assessed for any irrotational mean flow which approaches uniform axial flow far upstream. Sound spectra are presented for the case of two rotors in close proximity, for which the distortion is asymmetric. Quantities such as the turbulence spectrum at the rotor face and sound directivity then vary with azimuthal angle φ. © 2010 by Rosalyn A.V. Robison & N. Peake.

Rotor - Stator broadband noise prediction

In this paper a semi analytic model for rotor - stator broadband noise is presented. The work can be split into two sections. The first examines the distortion of the rotor wake in mean swirling flow, downstream of the fan. Previous work by Cooper and Peake4 is extended to include dissipative effects. In the second section we consider the interaction of this gust with the downstream stator row. We examine the way in which an unsteady pressure field is generated by the interaction of this wake flow with the stator blades and obtain estimates for the radiated noise. A new method is presented to extend the well known LINSUB code to the third dimension to capture the effect of the spanwise wavenumber and stator lean and sweep. Copyright © 2008 by Adrian Lloyd and Nigel Peake.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.