Off-wall boundary conditions for turbulent flows obtained from buffer-layer minimal flow units

There is strong evidence that the transport processes in the buffer region of wall-bounded turbulence are common across various flow configurations, even in the embryonic turbulence in transition (Park et al., Phys. Fl. 24). We use this premise to develop off-wall boundary conditions for turbulent simulations. Boundary conditions are constructed from DNS databases using periodic minimal flow units and reduced order modeling. The DNS data was taken from a channel at Reτ=400 and a zero-pressure gradient transitional boundary layer (Sayadi et al., submitted to J. Fluid Mech.). Both types of boundary conditions were first tested on a DNS of the core of the channel flow with the aim of extending their application to LES and to spatially evolving flows.

Effects of buffer layer properties and annealing process on bulk heterojunction morphology and organic solar cell performance

The performance of polymer-fullerene bulk heterojunction (BHJ) solar cells is strongly dependent on the vertical distribution of the donor and acceptor regions within the BHJ layer. In this work, we investigate in detail the effect of the hole transport layer (HTL) physical properties and the thermal annealing on the BHJ morphology and the solar cell performance. For this purpose, we have prepared solar cells with four distinct formulations of poly(3,4- ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) buffer layers. The samples were subjected to thermal annealing, applied either before (pre-annealing) or after (post-annealing) the cathode metal deposition. The effect of the HTL and the annealing process on the BHJ ingredient distribution - namely, poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl C61 butyric acid methyl ester (PCBM) - has been studied by spectroscopic ellipsometry and atomic force microscopy. The results revealed P3HT segregation at the top region of the films, which had a detrimental effect on all pre-annealed devices, whereas PCBM was found to accumulate at the bottom interface. This demixing process depends on the PEDOT:PSS surface energy; the more hydrophilic the surface the more profound is the vertical phase separation within the BHJ. At the same time those samples suffer from high recombination losses as evident from the analysis of the J-V measurements obtained in the dark. Our results underline the significant effect of the HTL-active and active-ETL (electron transport layer) interfacial composition that should be taken into account during the optimization of all polymer-fullerene solar cells. © 2012 The Royal Society of Chemistry.

GaN-based LEDs grown on 6-inch diameter Si (111) substrates by MOVPE

The issues and challenges of growing GaN-based structures on large area Si substrates have been studied. These include Si slip resulting from large temperature non-uniformities and cracking due to differential thermal expansion. Using an A1N nucleation layer in conjunction with an AlGaN buffer layer for stress management, and together with the interactive use of real time in-situ optical monitoring it was possible to realise flat, crack-free and uniform GaN and LED structures on 6-inch Si (111) substrates. The EL performance of processed LED devices was also studied on-wafer, giving good EL characteristics including a forward bias voltage of ∼3.5 V at 20 mA from a 500 μm × 500 μm device. © 2009 SPIE.

Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Structural and optical characterization of vertical GaAs/GaP core-shell nanowires grown on Si substrates

GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

Novel growth and properties of GaAs nanowires on Si substrates.

Straight, vertically aligned GaAs nanowires were grown on Si(111) substrates coated with thin GaAs buffer layers. We find that the V/III precursor ratio and growth temperature are crucial factors influencing the morphology and quality of buffer layers. A double layer structure, consisting of a thin initial layer grown at low V/III ratio and low temperature followed by a layer grown at high V/III ratio and high temperature, is crucial for achieving straight, vertically aligned GaAs nanowires on Si(111) substrates. An in situ annealing step at high temperature after buffer layer growth improves the surface and structural properties of the buffer layer, which further improves the morphology of the GaAs nanowire growth. Through such optimizations we show that vertically aligned GaAs nanowires can be fabricated on Si(111) substrates and achieve the same structural and optical properties as GaAs nanowires grown directly on GaAs(111)B substrates.

Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.

Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Destruction-free parameter extraction for a physics-based circuit simulator IGCT model

This paper presents a practical destruction-free parameter extraction methodology for a new physics-based circuit simulator buffer-layer Integrated Gate Commutated Thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results.

YBa2Cu3O7 tapes prepared by sol-gel deposition techniques: Microstructure and structural characterizations

We report on the preparation conditions of YBa2Cu3O7 polycrystalline superconducting tapes by a sol-gel deposition technique. We present some discussion on the compatibility between the nature of the substrate, the use of a buffer layer, and the conditions used to prepare appropriate superconducting YBa2Cu3O7 materials. We report also on the microstructural characterizations performed in order to evaluate the crystallites size, degree of orientation and connectivity. © 2002 Elsevier Science B.V. All rights reserved.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s. © 2014 AIP Publishing LLC.

Optical investigations of the effect of solvent and thermal annealing on the optoelectronic properties of Poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) films

Poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is one of the most promising conducting polymers that can be used as transparent electrode or as buffer layer for organic electronic devices. However, when used as an electrode, its conductivity has to be optimized either by the addition of solvents or by post-deposition processing. In this work, we investigate the effect of the addition of the polar solvent dimethylsulfoxide (DMSO) to an aqueous PEDOT:PSS solution on its optical and electrical properties by the implementation of the Drude model for the analysis of the measured pseudo-dielectric function by Spectroscopic Ellipsometry from the near infrared to the visible-far ultraviolet spectral range. The results show that the addition of DMSO increases significantly the film conductivity, which reaches a maximum value at an optimum DMSO concentration as it has confirmed by experimentally measured conductivity values. The post-deposition thermal annealing has been found to have a smaller effect on the film conductivity. © 2013 Elsevier B.V.