Laser microstructuring of Si surfaces for low-threshold field-electron emission

Dense arrays of high aspect ratio Si micro-pyramids have been formed by cumulative high intensity laser irradiation of doped Si wafers in an SF6 environment. A comparative study using nanosecond (XeCl, 308 nm) and femtosecond (Ti: Sapphire, 800 nm and KrF, 248 nm) laser pulses has been performed in this work. The influence of pulse duration and ambient gas pressure (SF6) is also presented. Scanning electron microscopy has shown that upon laser irradiation conical features appear on the Si surface in a rather homogenous distribution and with a spontaneous self alignment into arrays. Their lowest tip diameter is 800 nm; while their height reaches up to 90 mum. Secondary tip decoration appears on the surface of the formed spikes. Areas of 2 X 2 mm(2) covered with Si cones have been tested as cold cathode field emitters. After several conditioning cycles, the field emission threshold for the studied Si tips is as low as 2 V/mum, with an emission current of 10(-3) A/cm(2) at 4 V/mum. Even though these structures have smaller aspect ratios than good quality carbon nanotubes, their field emission properties are similar. The simple and direct formation of field emission Si arrays over small pre-selected areas by laser irradiation could lead to a novel approach for the development of electron sources. (C) 2003 Elsevier B.V. All rights reserved.

Evidence of quantum lateral confinement in side-gated resonant tunnelling diodes formed by patterned substrate regrowth

MBE regrowth on patterned np-GaAs wafers has been used to fabricate GaAs/AlGaAs double barrier resonant tunnel diodes with a side-gate in the plane of the quantum well. The physical diameters vary from 1 to 20 μm. For a nominally 1 μm diameter diode the peak current is reduced by more than 95% at a side-gate voltage of -2 V at 1.5 K, which we estimate corresponds to an active tunnel region diameter of 75 nm ± 10 nm. At high gate biases additional structure appears in the conductance data. Differential I-V measurements show a linear dependence of the spacing of subsidiary peaks on gate bias indicating lateral quantum confinement. © 1996 American Institute of Physics.

High current density nanofilament cathodes for microwave amplifiers

The fabrication of high current density nanofilament cathodes for microwave amplifiers was discussed. Metallic nanowires grown on silicon wafers and carbon nanotubes/nanofibers grown by catalytic plasma enhanced chemical vapor deposition (PECVD) were the two types of nanofilament arrays analyzed as cathodes materials. It was observed that the arrays of 5.8 μm height and 50 nm diameter carbon nanotubes exhibited geometrical enhancement factor of 240+-7.5%. The results show that carbon nanotubes/nanofibers arrays are best suited for nanofilament cathodes.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Vertically aligned carbon nanotubes growth using self-assembled Ni nanoparticles produced by ion implantation

An alternative method for seeding catalyst nanoparticles for carbon nanotubes and nanowires growth is presented. Ni nanoparticles are formed inside a 450 nm SiO2 film on (100) Si wafers through the implantation of Ni ions at fluences of 7.5×1015 and 1.7×1016 ions.cm-2 and post-annealing treatments at 700, 900 and 1100°C. After exposed to the surface by HF dip etching, the Ni nanoparticles are used as catalyst for the growth of vertically aligned carbon nanotubes by direct current plasma enhanced chemical vapor deposition. © 2007 Materials Research Society.

Thermal characterization of SOI CMOS micro hot-plate gas sensors

This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

On the percussion drilling of SI using a 20W MOPA based YB fiber laser

A study on the nanosecond fiber laser interaction with silicon was performed experimentally for the generation of percussion drilled holes. Single pulse ablation experiments were carried out on mono crystalline 650μm thick Si wafers. Changes of the mass removal mechanism were investigated by varying laser fluence up to 68 J/cm2 and pulse duration from 50 ns to 200 ns. Hole width and depth were measured and surface morphology were studied using scanning electron microscopy (SEM) and optical interferometric profilometry (Veeco NT3300). High speed photography was also used to examine laser generated plasma expansion rates. The material removal rate was found to be influenced by the pulse energy, full pulse duration and pulse peak power. Single pulse ablation depth of 4.42 μm was achieved using a 200 ns pulse of 13.3 J/cm 2, giving a maximum machining efficiency of 31.86 μm per mJ. Holes drilled with an increased fluence but fixed pulse length were deeper, exhibited low recast, but were less efficient than those produced at a lower fluence. The increased peak power in this case led to high levels of plasma and vapour production. The expansion of which, results in a strong driving recoil force, an increase in the rate and volume of melt ejection, and cleaner hole formation. The experimental findings show that for efficient drilling at a given energy, a longer, lower peak power pulse is more desirable than a high peak power short pulse.

Controllable chemical vapor deposition of large area uniform nanocrystalline graphene directly on silicon dioxide

Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.

Three dimensional distributions of arsenic and platinum within NiSi contact and gate of an n-type transistor

Atom probe tomography was used to study the redistribution of platinum and arsenic atoms after Ni(Pt) silicidation of As-doped polycrystalline Si. These measurements were performed on a field-effect transistor and compared with those obtained in unpatterned region submitted to the same process. These results suggest that Pt and As redistribution during silicide formation is only marginally influenced by the confinement in microelectronic devices. On the contrary, there is a clear difference with the redistribution reported in the literature for the blanket wafers. Selective etching used to remove the non-reacted Ni(Pt) film after the first rapid heat treatment may induce this difference. © 2011 American Institute of Physics.

Prospects of III-nitride optoelectronics grown on Si.

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

Low-cost high-efficiency GaN LED on large-area si substrate

The use of large size Si substrates for epitaxy of nitride light emitting diode (LED) structures has attracted great interest because Si wafers are readily available in large diameter at low cost. In addition, such wafers are compatible with existing processing lines for the 6-inch and larger wafer sizes commonly used in the electronics industry. With the development of various methods to avoid wafer cracking and reduce the defect density, the performance of GaN-based LED and electronic devices has been greatly improved. In this paper, we review our methods of growing crack-free InGaN-GaN multiple quantum well (MQW) LED structures of high crystalline quality on Si(111) substrates. The performance of processed LED devices and its dependence on the threading dislocation density were studied. Full wafer-level LED processing using a conventional 6-inch III-V processing line is also presented, demonstrating the great advantage of using large-size Si substrates for mass production of GaN LED devices.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.