Development of a classical force field for the oxidized Si surface: application to hydrophilic wafer bonding.

We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.

Post-CMOS wafer level growth of carbon nanotubes for low-cost microsensors--a proof of concept.

Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

Soft-lithographic processed soluble micropatterns of reduced graphene oxide for wafer-scale thin film transistors and gas sensors

PDMS based imprinting is firstly developed for patterning of rGO on a large area. High quality stripe and square shaped rGO patterns are obtained and the electrical properties of the rGO film can be adjusted by the concentration of GO suspension. The arrays of rGO electronics are fabricated from the patterned film by a simple shadow mask method. Gas sensors, which are based on these rGO electronics, show high sensitivity and recyclable usage in sensing NH 3. © 2012 The Royal Society of Chemistry.

Experimentally validated three dimensional GCT wafer level simulations

In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models. © 2012 IEEE.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

GaN-based LEDs grown on 6-inch diameter Si (111) substrates by MOVPE

The issues and challenges of growing GaN-based structures on large area Si substrates have been studied. These include Si slip resulting from large temperature non-uniformities and cracking due to differential thermal expansion. Using an A1N nucleation layer in conjunction with an AlGaN buffer layer for stress management, and together with the interactive use of real time in-situ optical monitoring it was possible to realise flat, crack-free and uniform GaN and LED structures on 6-inch Si (111) substrates. The EL performance of processed LED devices was also studied on-wafer, giving good EL characteristics including a forward bias voltage of ∼3.5 V at 20 mA from a 500 μm × 500 μm device. © 2009 SPIE.

Laser micromachining of thin films for optoelectronic devices and packages

Focused laser micromachining in an optical microscope system is used to prototype packages for optoelectronic devices and to investigate new materials with potential applications in packaging. Micromachined thin films are proposed as mechanical components to locate fibres and other optical and electrical components on opto-assemblies. This paper reports prototype structures which are micromachined in silicon carbide to produce beams 5 μm thick by (i) laser cutting a track in a SiC coated Si wafer, (ii) undercutting by anisotropic silicon etching using KOH in water, and (iii) trimming if necessary with the laser system. This approach has the advantage of fast turn around and proof of concept. Mechanical test data are obtained from the prototype SiC beam package structures by testing with a stylus profilometer. The Youngs modulus obtained for chemical vapour deposited silicon carbide is 360 +/- 50 GPa indicating that it is a promising material for packaging applications.

Fabrication of diamond based schottky barrier diodes with oxide ramp termination

The paper's goal is the first demonstration of the fabrication of high power Schottky diodes on synthetic diamond using oxide ramp termination. In order to allow full activated impurities at room temperature and a high hole mobility a low boron doping of the drift layer is employed. Several aspects of the manufacturing technology are presented. A termination with a small ramp angle can be obtained using only RIE technique due to diamond wafer nonuniformity (roughness). Experimental forward and reverse characteristics measured on diamond diodes are also included. © 2007 IEEE.

On-chip deposition of carbon nanotubes using CMOS microhotplates.

The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.