Solid-state memories based on ferroelectric tunnel junctions

Ferroic-order parameters are useful as state variables in non-volatile information storage media because they show a hysteretic dependence on their electric or magnetic field. Coupling ferroics with quantum-mechanical tunnelling allows a simple and fast readout of the stored information through the influence of ferroic orders on the tunnel current. For example, data in magnetic random-access memories are stored in the relative alignment of two ferromagnetic electrodes separated by a non-magnetic tunnel barrier, and data readout is accomplished by a tunnel current measurement. However, such devices based on tunnel magnetoresistance typically exhibit OFF/ON ratios of less than 4, and require high powers for write operations (>1 × 10 6 A cm -2). Here, we report non-volatile memories with OFF/ON ratios as high as 100 and write powers as low as ∼1 × 10 4A cm -2 at room temperature by storing data in the electric polarization direction of a ferroelectric tunnel barrier. The junctions show large, stable, reproducible and reliable tunnel electroresistance, with resistance switching occurring at the coercive voltage of ferroelectric switching. These ferroelectric devices emerge as an alternative to other resistive memories, and have the advantage of not being based on voltage-induced migration of matter at the nanoscale, but on a purely electronic mechanism. © 2012 Macmillan Publishers Limited. All rights reserved.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.