The effect of an insoluble surfactant on the skin friction of a bubble

In this paper, we develop a novel moving mesh method suitable for solving axisymmetric free-boundary problems, including the Marangoni effect induced by surfactant or temperature variation. This method employs a body-fitted grid system where the gas-liquid interface is one line of the grid system. We model the surfactant equation of state with a non-linear Langmuir law, and, for simplicity, we limit ourselves to the situation of an insoluble surfactant. We solve complicated dynamic boundary conditions accurately on the gas-liquid interface in the framework of finite-volume methods. Our method is used to study the effect of a surfactant on the skin friction of a bubble in a uniaxial flow. For the limiting case where the surface diffusivity is zero, the effect of a tangential stress generated by the surface tension gradient, allows us to explain a new phenomenon in high concentration regimes: larger surface tension, but also larger deformation. Furthermore, this condition leads to the formation of boundary layers and flow separation at high Reynolds numbers. The influence of these complex flow patterns is examined. © 2005 Elsevier SAS. All rights reserved.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Microstructural modelling in friction stir welding of 2000 series aluminium alloys

Simple process models are applied to predict microstructural changes due to the thermal cycle imposed in friction stir welding. A softening model developed for heat-treatable aluminium alloys of the 6000 series is applied to the aerospace alloy 2014 in the peak-aged (T6) condition. It is found that the model is not readily applicable to alloy 2024 in the naturally aged (T3) temper, but the softening behaviour can still be described semi-empirically. Both analytical and numerical (finite element) thermal models are used to predict the thermal histories in trial welds. These are coupled to the microstructural model to investigate: (a) the hardness profile across the welded plate; (b) alloy softening ahead of the approaching welding tool. By incorporating the softening model applied to 6082-T6 alloy, the hardness profile of friction stir welds in dissimilar alloys is also predicted. © AFM, EDP Sciences 2005.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.