Passive suspensions incorporating inerters for railway vehicles

This paper investigates the possibility of improving the performance of railway vehicle suspensions by incorporating a newly developed mechanical device known as the inerter. A comparative study of several low-complexity passive suspension layouts is made. Improved performance for the lateral and vertical ride comfort, as well as lateral body movement when curving are demonstrated in comparison with the conventional suspension layout. The constraints imposed are to maintain the same level of other performance metrics. The calculations and optimisations are based on linearised plan-view and side-view high-speed train mathematical models. © 2012 Copyright Taylor and Francis Group, LLC.

Increasing allowable deformation criteria through application of level II LTSM approach

In the central part of the Delft railway tunnel project, an underground railway station is being built at very close distance to the existing station building, which is still in operation. Although elaborate sensitivity analyses were made, some unforeseen deformations were encountered during the first phases of the execution process. Especially the installation of temporary sheet pile walls as well as the installation of a huge amount of grout anchor piles resulted in deformations exceeding the predicted final deformations as well as the boundary values defined by a level I limiting tensile strain method (LTSM) approach. In order to ensure the execution process, supplementary analyses were made to predict future deformations, and this for multiple cross sections. These deformations were implemented into a finite element model of the masonry of the building in order to define probable crack formation. This Level II LTSM approach made it possible to increase the initially foreseen deformation criteria and the continuation of the works. Design steps, design models and monitoring results will be explained within this paper.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Patterning and detailed study of human hNT astrocytes on parylene-C/silicon dioxide substrates to the single cell level.

It is estimated that the adult human brain contains 100 billion neurons with 5-10 times as many astrocytes. Although it has been generally considered that the astrocyte is a simple supportive cell to the neuron, recent research has revealed new functionality of the astrocyte in the form of information transfer to neurons of the brain. In our previous work we developed a protocol to pattern the hNT neuron (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/SiO(2) substrates. In this work, we report how we have managed to pattern hNT astrocytes, on parylene-C/SiO(2) substrates to single cell resolution. This article disseminates the nanofabrication and cell culturing steps necessary for the patterning of such cells. In addition, it reports the necessary strip lengths and strip width dimensions of parylene-C that encourage high degrees of cellular coverage and single cell isolation for this cell type. The significance in patterning the hNT astrocyte on silicon chip is that it will help enable single cell and network studies into the undiscovered functionality of this interesting cell, thus, contributing to closer pathological studies of the human brain.