9 resultados para Preparation methods for cerium oxide

em Cambridge University Engineering Department Publications Database


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Different FIB-based sample preparation methods for atom probe analysis of transistors have been proposed and discussed. A special procedure, involving device deprocessing, has been used to analyze by APT a sub-30 nm transistor extracted from a SRAM device. The analysis provides three dimensional compositions of Ni-silicide contact, metal gate and high-k oxide of the transistor gate. © 2013 Elsevier B.V. All rights reserved.

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An X-ray imaging technique is used to probe the stability of 3-dimensional granular packs in a slowly rotating drum. Well before the surface reaches the avalanche angle, we observe intermittent plastic events associated with collective rearrangements of the grains located in the vicinity of the free surface. The energy released by these discrete events grows as the system approaches the avalanche threshold. By testing various preparation methods, we show that the pre-avalanche dynamics is not solely controlled by the difference between the free surface inclination and the avalanche angle. As a consequence, the measure of the pre-avalanche dynamics is unlikely to serve as a tool for predicting macroscopic avalanches.

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Through silicon via (TSV) technology is key for next generation three-dimensional integrated circuits, and carbon nanotubes (CNT) provide a promising alternative to metal for filling the TSV. Three catalyst preparation methods for achieving CNT growth from the bottom of the TSV are investigated. Compared with sputtering and evaporation, catalyst deposition using dip-coating in a FeCl2 solution is found to be a more efficient method for realizing a bottom-up filling of the TSV (aspect ratio 5 or 10) with CNT. The CNT bundles grown in 5 min exceed the 50 μm length of the TSV and are multi-wall CNT with three to eight walls. The CNT bundles inside the TSV were electrically characterized by creating a direct contact using a four-point nanoprober setup. A low resistance of the CNT bundle of 69.7 Ω (297 Ω) was measured when the CNT bundle was contacted midway along (over the full length of) the 25 μm deep TSV. The electrical characterization in combination with the good filling of the TSV demonstrates the potential use of CNT in fully integrated TSV applications.

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Controlling the growth of ZnO nanostructures for photovoltaic applications will ensure greater device efficiency and parameter control. This paper reports on methods to engineer the morphology and tailor the nanostructure growth direction through the hydrothermal synthesis method. Effective control is achieved through the use of a sputtered zinc layer together with modifications of the growth solution. These nanostructures have been developed with a view to incorporation into excitonic solar cells, and methods to improve surface stability using a fully aqueous synthesis method will be discussed. © by Oldenbourg Wissenschaftsverlag, München.

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We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi 2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi 2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs. © 2012 American Institute of Physics.

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In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.

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Synthesis of polycationic compounds by the spray-drying technique is an interesting alternative in the domain of aqueous precursor synthesis methods. Spray drying yields high quality samples with good reproducibility. The possibility of scaling up for production of large quantities with fast processing time is well established by the commercial availability of powders of various compositions. In this paper, we have discussed the advantages and limitations of this method and demonstrated its interest by synthesizing a few polycationic compounds selected for their attractive properties of thermoelectricity [Bi1.68Ca2Co1.69O 8, La0.95A0.05CoO3 (A=Ca, Sr, Ba)] or magnetoresistance [La0.70A0.30MnO3 (A=Sr, Ba)]. We have confirmed the quality of these samples by reporting their structure, magnetic and transport properties. © 2010 Elsevier Ltd All rights reserved.