The environmental and economic sustainability of potential bioethanol from willow in the UK.

Life cycle assessment has been used to investigate the environmental and economic sustainability of a potential operation in the UK in which bioethanol is produced from the hydrolysis and subsequent fermentation of coppice willow. If the willow were grown on idle arable land in the UK, or, indeed, in Eastern Europe and imported as wood chips into the UK, it was found that savings of greenhouse gas emissions of 70-90%, when compared to fossil-derived gasoline on an energy basis, would be possible. The process would be energetically self-sufficient, as the co-products, e.g. lignin and unfermented sugars, could be used to produce the process heat and electricity, with surplus electricity being exported to the National Grid. Despite the environmental benefits, the economic viability is doubtful at present. However, the cost of production could be reduced significantly if the willow were altered by breeding to improve its suitability for hydrolysis and fermentation.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

SUB-BAND CODING TECHNIQUES FOR ROBUST 4. 8 TO 8 kb/s SPEECH CODERS.

This paper describes a speech coding technique that has been developed in order to provide a method of digitising speech at bit rates in the range 4. 8 to 8 kb/s, that is insensitive to the effects of acoustic background noise and bit errors on the digital link. The main aim has been to develop a coding scheme which provides speech quality and robustness against noise and errors that is similar to a 16000 b/s continuously variable slope delta (CVSD) coder, but which operates at half its data rate or less. A desirable aim was to keep the complexity of the coding scheme within the scope of what could reasonably be handled by current signal processing chips or by a single custom integrated circuit. Applications areas include mobile radio and small Satcomms terminals.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Wavelength tunable graphene modelocked VECSEL

We passively modelock an optically pumped VECSEL by using a single-layer graphene saturable absorber mirror, resulting in pulses as short as 473 fs. A broad wavelength tuning range of 46 nm is achieved with three different VECSEL chips, with a single chip 21 nm are covered. © OSA 2013.

16 chip, 18 Gchips/s walsh-code implementation of an ECDMA access network using two time-shifted FIR filters

We demonstrate for the first time an electronically processed Walsh Code with 16 chips at 18Gchip/s. An auto-cross correlation ratio of 18.1dB is achieved between two orthogonal codes after transmission over 10km of SMF. © 2009 OSA.

A low latency optical top of rack switch for data centre networks with minimized processor energy load

We propose a low latency optical data center top of rack switch using recirculation buffering and a hybrid MZ/SOA switch architecture to reduce the network power dissipated on future optically connected server chips by 53%. © OSA 2014.

Graphene modelocked VECSELs

In the past decade, passively modelocked optically pumped vertical external cavity surface emitting lasers (OPVECSELs), sometimes referred to as semiconductor disk lasers (OP-SDLs), impressively demonstrated the potential for generating femtosecond pulses at multi-Watt average output powers with gigahertz repetition rates. Passive modelocking with a semiconductor saturable absorber mirror (SESAM) is well established and offers many advantages such as a flexible design of the parameters and low non-saturable losses. Recently, graphene has emerged as an attractive wavelength-independent alternative saturable absorber for passive modelocking in various lasers such as fiber or solid-state bulk lasers because of its unique optical properties. Here, we present and discuss the modelocked VECSELs using graphene saturable absorbers. The broadband absorption due to the linear dispersion of the Dirac electrons in graphene makes this absorber interesting for wavelength tunable ultrafast VECSELs. Such widely tunable modelocked sources are in particularly interesting for bio-medical imaging applications. We present a straightforward approach to design the optical properties of single layer graphene saturable absorber mirrors (GSAMs) suitable for passive modelocking of VECSELs. We demonstrate sub-500 fs pulses from a GSAM modelocked VECSEL. The potential for broadband wavelength tuning is confirmed by covering 46 nm in modelocked operation using three different VECSEL chips and up to 21 nm tuning in pulsed operation is achieved with one single gain chip. A linear and nonlinear optical characterization of different GSAMs with different absorption properties is discussed and can be compared to SESAMs. © 2014 SPIE.