Potential tuning of porous silicon luminescence

Electrochemical investigations were conducted of the effect of potential on the luminescence of porous silico (PS). The use of liquid contacts allows the potential to be controlled during studies of the photoluminescence (PL) and electroluminescence (EI). The PL and EL of PS samples prepared from n-type substrates is considered. To obtain luminescence from such PS it is necessary to generate holes in the valence band. This is achieved by either photoexcitation or an electrochemical process involving the reduction of persulfate. This paper describes the investigations of the effect of potential on the PL and EL of PS. A mechanism of 'potential tuning' based on electron occupancy and Auger quenching is then proposed.

High speed liquid crystal over silicon display based on the flexoelectro-optic effect.

One of the key technologies to evolve in the displays market in recent years is liquid crystal over silicon (LCOS) microdisplays. Traditional LCOS devices and applications such as rear projection televisions, have been based on intensity modulation electro-optical effects, however, recent developments have shown that multi-level phase modulation from these devices is extremely sought after for applications such as holographic projectors, optical correlators and adaptive optics. Here, we propose alternative device geometry based on the flexoelectric-optic effect in a chiral nematic liquid crystal. This device is capable of delivering a multilevel phase shift at response times less than 100 microsec which has been verified by phase shift interferometry using an LCOS test device. The flexoelectric on silicon device, due to its remarkable characteristics, enables the next generation of holographic devices to be realized.

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.

First human hNT neurons patterned on parylene-C/silicon dioxide substrates: Combining an accessible cell line and robust patterning technology for the study of the pathological adult human brain

In this communication, we describe a new method which has enabled the first patterning of human neurons (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/silicon dioxide substrates. We reveal the details of the nanofabrication processes, cell differentiation and culturing protocols necessary to successfully pattern hNT neurons which are each key aspects of this new method. The benefits in patterning human neurons on silicon chip using an accessible cell line and robust patterning technology are of widespread value. Thus, using a combined technology such as this will facilitate the detailed study of the pathological human brain at both the single cell and network level. © 2010 Elsevier B.V.

Porous materials for thermal management under extreme conditions

A brief analysis is presented of how heat transfer takes place in porous materials of various types. The emphasis is on materials able to withstand extremes of temperature, gas pressure, irradiation, etc., i.e. metals and ceramics, rather than polymers. A primary aim is commonly to maximize either the thermal resistance (i.e. provide insulation) or the rate of thermal equilibration between the material and a fluid passing through it (i.e. to facilitate heat exchange). The main structural characteristics concern porosity (void content), anisotropy, pore connectivity and scale. The effect of scale is complex, since the permeability decreases as the structure is refined, but the interfacial area for fluid-solid heat exchange is, thereby, raised. The durability of the pore structure may also be an issue, with a possible disadvantage of finer scale structures being poor microstructural stability under service conditions. Finally, good mechanical properties may be required, since the development of thermal gradients, high fluid fluxes, etc. can generate substantial levels of stress. There are, thus, some complex interplays between service conditions, pore architecture/scale, fluid permeation characteristics, convective heat flow, thermal conduction and radiative heat transfer. Such interplays are illustrated with reference to three examples: (i) a thermal barrier coating in a gas turbine engine; (ii) a Space Shuttle tile; and (iii) a Stirling engine heat exchanger. Highly porous, permeable materials are often made by bonding fibres together into a network structure and much of the analysis presented here is oriented towards such materials. © 2005 The Royal Society.

Efficiency measurement of GaN-based quantum well and light-emitting diode structures grown on silicon substrates

The optical efficiency of GaN-based multiple quantum well (MQW) and light emitting diode (LED) structures grown on Si(111) substrates by metal-organic vapor phase epitaxy was measured and compared with equivalent structures on sapphire. The crystalline quality of the LED structures was comprehensively characterized using x-ray diffraction, atomic force microscopy, and plan-view transmission electron microscopy. A room temperature photoluminescence (PL) internal quantum efficiency (IQE) as high as 58% has been achieved in an InGaN/GaN MQW on Si, emitting at 460 nm. This is the highest reported PL-IQE of a c-plane GaN-based MQW on Si, and the radiative efficiency of this sample compares well with similar structures grown on sapphire. Processed LED devices on Si also show good electroluminescence (EL) performance, including a forward bias voltage of ∼3.5 V at 20 mA and a light output power of 1 mW at 45 mA from a 500 ×500 μm2 planar device without the use of any additional techniques to enhance the output coupling. The extraction efficiency of the LED devices was calculated, and the EL-IQE was then estimated to have a maximum value of 33% at a current density of 4 A cm-2, dropping to 30% at a current density of 40 A cm-2 for a planar LED device on Si emitting at 455 nm. The EL-IQE was clearly observed to increase as the structural quality of the material increased for devices on both sapphire and Si substrates. © 2011 American Institute of Physics.

Assembly and inspection of liquid crystal on silicon devices

Liquid crystal on silicon (LCOS) is one of the most exciting technologies, combining the optical modulation characteristics of liquid crystals with the power and compactness of a silicon backplane. The objective of our work is to improve cell assembly and inspection methods by introducing new equipment for automated assembly and by using an optical inspection microscope. A Suss-Micro'Tec Universal device bonder is used for precision assembly and device packaging and an Olympus BX51 high resolution microscope is employed for device inspection. ©2009 Optical Society of America.