Low short term timing jitter in an integrated monolithic extended cavity semiconductor mode-locked laser

Jitter measurements were performed on a monolithically integrated active/passive cavity multiple quantum well laser, actively mode-locked at 10 GHz via modulation of an absorber section. Sub-10 ps pulses were produced upon optimization of the drive conditions to the gain, distributed Bragg reflector, and absorber sections. A model was also developed using travelling wave rate equations. Simulation results suggest that spontaneous emission is the dominant cause of jitter, with carrier dynamics having a time constant of the order of 1 ns.

Study of high performance Re-timing using a 40 Gb/s hybrid-integrated mach-zehnder all-optical regenerator

We experimentally show that a hybrid-integrated Mach-Zehnder switch with a high performance gate profile allows retiming of optical signals with an accuracy of 500-700fs even if the input timing jitter is increased to 3ps. © 2004 Optical Society of America.

Study of high performance re-timing using a 40 Gb/s hybrid-integrated mach-zehnder all-optical regenerator

We experimentally show that a hybrid-integrated Mach-Zehnder switch with a high performance gate profile allows retiming of optical signals with an accuracy of 500-700fs even if the input timing jitter is increased to 3ps. © 2004 Optical Society of America.

100 Gigabit Ethernet transmission enabled by carrierless amplitude and phase modulation using QAM receivers

Simulations have investigated single laser 100G Ethernet links enabled by CAP-16 using QAM receivers that not only lower significantly system timing jitter sensitivity but also outperform PAM and standard CAP in terms of power margin. © 2013 OSA.

100 Gigabit ethernet transmission enabled by carrierless amplitude and phase modulation using QAM receivers

Simulations have investigated single laser 100G Ethernet links enabled by CAP-16 using QAM receivers that not only lower significantly system timing jitter sensitivity but also outperform PAM and standard CAP in terms of power margin. © 2013 OSA.

Sub-kHz RF electrical linewidth from a 10GHz passively mode-locked quantum-dot laser diode

A packaged 10GHz monolithic two-section quantum-dot mode-locked laser is presented, with record narrow 500Hz RF electrical linewidth for passive mode-locking. Single sideband noise spectra show 147fs integrated timing jitter over the 4MHz-80MHz frequency range. © 2009 Optical Society of America.

Correct biological timing in Arabidopsis requires multiple light-signaling pathways.

Circadian oscillators provide rhythmic temporal cues for a range of biological processes in plants and animals, enabling anticipation of the day/night cycle and enhancing fitness-associated traits. We have used engineering models to understand the control principles of a plant's response to seasonal variation. We show that the seasonal changes in the timing of circadian outputs require light regulation via feed-forward loops, combining rapid light-signaling pathways with entrained circadian oscillators. Linear time-invariant models of circadian rhythms were computed for 3,503 circadian-regulated genes and for the concentration of cytosolic-free calcium to quantify the magnitude and timing of regulation by circadian oscillators and light-signaling pathways. Bioinformatic and experimental analysis show that rapid light-induced regulation of circadian outputs is associated with seasonal rephasing of the output rhythm. We identify that external coincidence is required for rephasing of multiple output rhythms, and is therefore important in general phase control in addition to specific photoperiod-dependent processes such as flowering and hypocotyl elongation. Our findings uncover a fundamental design principle of circadian regulation, and identify the importance of rapid light-signaling pathways in temporal control.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Hierarchical approach to timing verification in CMOS VLSI design

This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.