1.4 kV, 25 A, PT and NPT Trench IGBTs with optimum forward characteristics

In this paper we report the development of 1.4 kV 25 A PT and NPT Trench IGBTs with ultra-low on-resistance, latch-up free operation and highly superior overall performance when compared to previously reported DMOS IGBTs in the same class. We have fabricated both PT and transparent anode NPT devices to cover a wide range of applications which require very low on-state losses or very fast time with ultra-low switching losses. The minimum forward voltage drop at the standard current density of 100A/cm2 was 1.1 V for PT non-irradiated devices and 2.1 V for 16 MRad PT irradiated devices. The non-irradiated transparent emitter NPT structure has a typical forward voltage drop of 2.2 V, a turn-off time below 100 ns and turn-off energy losses of 11.2 mW/cm2 at 125 C. The maximum controllable current density was in excess of 1000A/cm2.

Pt redistribution in N-MOS transistors during Ni salicide process

Atom probe tomography was used to study the redistribution of platinum during Ni(10 at.%Pt) silicidation of n-doped polycrystalline Si. These measurements were performed after the two annealing steps of standard salicide process both on a field-effect transistor and on unpatterned region submitted to the same process. Very similar results are obtained in unpatterned region and in transistor gate contact. The first phase to form is not the expected δ-Ni2Si but the non stoichiometric θ-Ni2Si. Pt redistribution is strongly influenced by this phase and the final distribution is different from what is reported in literature. © 2013 Elsevier B.V. All rights reserved.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.