Parasitic feedthrough cancellation techniques for enhanced electrical characterization of electrostatic microresonators

Capacitive parasitic feedthrough is an impediment that is inherent to all electrically interfaced micron scale resonant devices, resulting in increased challenges to their integration in more complex circuits, particularly as devices are scaled to operate at higher frequencies for RF applications. In this paper, a technique to cancel the undesirable effects of capacitive feedthrough that was previously proposed is here developed for an on-chip implementation. The method reported in this paper benefits from the simplicity of its implementation, and its effectiveness is demonstrated in this paper. This technique is demonstrated for two disk-plate resonators that have been excited in the wine glass mode at 5.4 MHz, though applicable to almost any electrically interfaced resonator. Measurements of the electrical transmission from these resonators show that the magnitude of the frequency response of the system is enhanced by up to 19 dB, while the phase is found to shift through a full 180° about the resonant frequency. This method is proposed as a useful addition to other techniques for enhancing the measured response of electrostatic micromechanical resonators. © 2009 Elsevier B.V. All rights reserved.

Enhanced transduction methods for electrostatically driven MEMS resonators

Electrically addressed silicon bulk acoustic wave microresonators offer high Q solutions for applications in sensing and signal processing. However, the electrically transduced motional signal is often swamped by parasitic feedthrough in hybrid technologies. With the aim of enhancing the ratio of the motional to feedthrough current at nominal operating voltages, this paper benchmarks a variety of drive and detection principles for electrostatically driven square-extensional mode resonators operating in air and in a foundry MEMS process utilizing 2μm gaps. A new detection technique, combining second harmonic capacitive actuation and piezoresistive detection, outperforms previously reported methods utilizing voltages as low as ± 3V in air providing a promising solution for low voltage CMOS-MEMS integration. ©2009 IEEE.

Direct parameter extraction in feedthrough-embedded capacitive MEMS resonators

This paper presents a method for fast and accurate determination of parameters relevant to the characterization of capacitive MEMS resonators like quality factor (Q), resonant frequency (fn), and equivalent circuit parameters such as the motional capacitance (Cm). In the presence of a parasitic feedthrough capacitor (CF) appearing across the input and output ports, the transmission characteristic is marked by two resonances: series (S) and parallel (P). Close approximations of these circuit parameters are obtained without having to first de-embed the resonator motional current typically buried in feedthrough by using the series and parallel resonances. While previous methods with the same objective are well known, we show that these are limited to the condition where CF ≪ CmQ. In contrast, this work focuses on moderate capacitive feedthrough levels where CF > CmQ, which are more common in MEMS resonators. The method is applied to data obtained from the measured electrical transmission of fabricated SOI MEMS resonators. Parameter values deduced via direct extraction are then compared against those obtained by a full extraction procedure where de-embedding is first performed and followed by a Lorentzian fit to the data based on the classical transfer function associated with a generic LRC series resonant circuit. © 2011 Elsevier B.V. All rights reserved.

p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration

A novel CMOS compatible lateral thyristor is proposed in this paper. Its thyristor conduction is fully controlled by a p-MOS gate. Loss of MOS control due to parasitic latch-up has been eliminated and triggering of the main thyristor at lower forward current achieved. The device operation has been verified by 2-D numerical simulations and experimental fabrication.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Advantage of superconducting bearing in a commercial flywheel system

The use of a superconducting magnetic bearing in an Urenco Power Technologies (UPT) 100kW flywheel is being studied. The dynamics of a conventional flywheel energy storage system have been studied at low frequencies. We show that the main design consideration is overcoming drag friction losses and parasitic resonances. We propose an original superconducting magnetic bearing design and improved cryogenic motor cooling to increase stability and decrease energy losses in the system. © 2008 IOP Publishing Ltd.

Loss comparison between an SPWM and harmonic elimination excited small, (<1kW) induction motor drive using Pspice simulation and calorimetry

Adopting square wave excitation to drive induction motors (IMs) can substantially reduce inverter switching losses. However, the low-order time harmonics inherent in the output voltage generates parasitic torques that degrade motor performance and reduce efficiency. In this paper, a novel harmonic elimination modulation technique with full voltage control is studied as an interesting and alternative means of operating small (<1kW) IM drives efficiently. A fully verified harmonic elimination scheme, which removes the 5th, 7th, 11th, 13th and 17 th time harmonics, was implemented and applied to an IGBT driven IM. The power losses incurred in the inverter and the IM as a result of the switching scheme have been determined. © 2008 Crown copyright.

Spice modelling of the superjunction IGBT

This paper presents a SPICE model of the SuperJunction Insulated Gate Bipolar Transistor (SJIGBT) [1]. SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.