28 resultados para Oxidized starch
em Cambridge University Engineering Department Publications Database
Resumo:
We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.
Resumo:
We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.
Resumo:
We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 IEEE.
Resumo:
We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 OSA.
Resumo:
We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip. © 2011 American Chemical Society.
Resumo:
We experimentally demonstrate a self-aligned approach for the fabrication of nanoscale hybrid silicon-plasmonic waveguide fabricated by local oxidation of silicon (LOCOS). Implementation of the LOCOS technique provides compatibility with standard complementary metal-oxide-semiconductor technology and allows avoiding lateral misalignment between the silicon waveguide and the upper metallic layer. We directly measured the propagation and the coupling loss of the fabricated hybrid waveguide using a near-field scanning optical microscope. The demonstrated structure provides nanoscale confinement of light together with a reasonable propagation length of ∼100 μm. As such, it is expected to become an important building block in future on-chip optoelectronic circuitry. © 2010 American Institute of Physics.
Resumo:
We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 Optical Society of America.
Resumo:
We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. ©2011 Optical Society of America.
Resumo:
We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 Optical Society of America.
Resumo:
We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 Optical Society of America.
Resumo:
A systematic study of the kinetics of axial Ni silicidation of as-grown and oxidized Si nanowires (SiNWs) with different crystallographic orientations and core diameters ranging from ∼ 10 to 100 nm is presented. For temperatures between 300 and 440 °C the length of the total axial silicide intrusion varies with the square root of time, which provides clear evidence that the rate limiting step is diffusion of Ni through the growing silicide phase(s). A retardation of Ni-silicide formation for oxidized SiNWs is found, indicative of a stress induced lowering of the diffusion coefficients. Extrapolated growth constants indicate that the Ni flux through the silicided NW is dominated by surface diffusion, which is consistent with an inverse square root dependence of the silicide length on the NW diameter as observed for (111) orientated SiNWs. In situ TEM silicidation experiments show that NiSi(2) is the first forming phase for as-grown and oxidized SiNWs. The silicide-SiNW interface is thereby atomically abrupt and typically planar. Ni-rich silicide phases subsequently nucleate close to the Ni reservoir, which for as-grown SiNWs can lead to a complete channel break-off for prolonged silicidation due to significant volume expansion and morphological changes.
Resumo:
A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.