Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 IEEE.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip. © 2011 American Chemical Society.

Locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip locally-oxidized silicon surface-plasmon Schottky detector for telecom wavelengths based on the internal photoemission process. Theoretical model and experimental results will be presented and discussed. © 2011 Optical Society of America.

Controllable chemical vapor deposition of large area uniform nanocrystalline graphene directly on silicon dioxide

Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.

High current density nanofilament cathodes for microwave amplifiers

The fabrication of high current density nanofilament cathodes for microwave amplifiers was discussed. Metallic nanowires grown on silicon wafers and carbon nanotubes/nanofibers grown by catalytic plasma enhanced chemical vapor deposition (PECVD) were the two types of nanofilament arrays analyzed as cathodes materials. It was observed that the arrays of 5.8 μm height and 50 nm diameter carbon nanotubes exhibited geometrical enhancement factor of 240+-7.5%. The results show that carbon nanotubes/nanofibers arrays are best suited for nanofilament cathodes.

Experimental demonstration of locally oxidized hybrid silicon-plasmonic waveguide

We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 OSA.

Experimental demonstration of locally oxidized hybrid silicon-plasmonic waveguide

We experimentally demonstrate a self-aligned approach for the fabrication of nanoscale hybrid silicon-plasmonic waveguide fabricated by local oxidation of silicon (LOCOS). Implementation of the LOCOS technique provides compatibility with standard complementary metal-oxide-semiconductor technology and allows avoiding lateral misalignment between the silicon waveguide and the upper metallic layer. We directly measured the propagation and the coupling loss of the fabricated hybrid waveguide using a near-field scanning optical microscope. The demonstrated structure provides nanoscale confinement of light together with a reasonable propagation length of ∼100 μm. As such, it is expected to become an important building block in future on-chip optoelectronic circuitry. © 2010 American Institute of Physics.

Experimental demonstration of locally oxidized hybrid silicon-plasmonic waveguide

We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 Optical Society of America.

Experimental demonstration of locally oxidized hybrid silicon-plasmonic waveguide

We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. ©2011 Optical Society of America.

Experimental demonstration of locally oxidized hybrid silicon-plasmonic waveguide

We demonstrate self-aligned approach for fabrication of hybrid silicon plasmonic waveguide. The demonstrated structure provides both nanoscale confinement together with propagation length of 100 microns. Near-field measurements of propagation and coupling loss are also presented. © 2011 Optical Society of America.

Development of a classical force field for the oxidized Si surface: application to hydrophilic wafer bonding.

We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

High speed liquid crystal over silicon display based on the flexoelectro-optic effect.

One of the key technologies to evolve in the displays market in recent years is liquid crystal over silicon (LCOS) microdisplays. Traditional LCOS devices and applications such as rear projection televisions, have been based on intensity modulation electro-optical effects, however, recent developments have shown that multi-level phase modulation from these devices is extremely sought after for applications such as holographic projectors, optical correlators and adaptive optics. Here, we propose alternative device geometry based on the flexoelectric-optic effect in a chiral nematic liquid crystal. This device is capable of delivering a multilevel phase shift at response times less than 100 microsec which has been verified by phase shift interferometry using an LCOS test device. The flexoelectric on silicon device, due to its remarkable characteristics, enables the next generation of holographic devices to be realized.