Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Analysis of switched capacitor DC-DC step down converter

A 5V/1 V Switched Capacitor (SC) dc-dc converter designed for a 0.18μm CMOS process is analysed in detail, in this paper. Analytical equations are derived for the voltages and currents through the main components of the SC converter. The model includes switches, capacitors, equivalent series resistances and the load. The switches in the converter are represented by MOSFETs in the UMC 0.18μm CMOS process. The impact of system parameters on output voltage ripple are studied using the analytical expressions.

Single sensor boost converter-based maximum power point tracking algorithms

Two new maximum power point tracking algorithms are presented: the input voltage sensor, and duty ratio maximum power point tracking algorithm (ViSD algorithm); and the output voltage sensor, and duty ratio maximum power point tracking algorithm (VoSD algorithm). The ViSD and VoSD algorithms have the features, characteristics and advantages of the incremental conductance algorithm (INC); but, unlike the incremental conductance algorithm which requires two sensors (the voltage sensor and current sensor), the two algorithms are more desirable because they require only one sensor: the voltage sensor. Moreover, the VoSD technique is less complex; hence, it requires less computational processing. Both the ViSD and the VoSD techniques operate by maximising power at the converter output, instead of the input. The ViSD algorithm uses a voltage sensor placed at the input of a boost converter, while the VoSD algorithm uses a voltage sensor placed at the output of a boost converter. © 2011 IEEE.

Loss comparison between an SPWM and harmonic elimination excited small, (<1kW) induction motor drive using Pspice simulation and calorimetry

Adopting square wave excitation to drive induction motors (IMs) can substantially reduce inverter switching losses. However, the low-order time harmonics inherent in the output voltage generates parasitic torques that degrade motor performance and reduce efficiency. In this paper, a novel harmonic elimination modulation technique with full voltage control is studied as an interesting and alternative means of operating small (<1kW) IM drives efficiently. A fully verified harmonic elimination scheme, which removes the 5th, 7th, 11th, 13th and 17 th time harmonics, was implemented and applied to an IGBT driven IM. The power losses incurred in the inverter and the IM as a result of the switching scheme have been determined. © 2008 Crown copyright.

Use of a high-temperature superconducting coil for magnetic energy storage

A high temperature superconducting magnetic energy storage device (SMES) has been realised using a 350 m-long BSCCO tape wound as a pancake coil. The coil is mounted on a cryocooler allowing temperatures down to 17.2 K to be achieved. The temperature dependence of coil electrical resistance R(T) shows a superconducting transition at T 102.5 K. Measurements of the V(I) characteristics were performed at several temperatures between 17.2 K and 101.5 K to obtain the temperature dependence of the critical current (using a 1 νV/cm criterion). Critical currents were found to exceed 100 A for T < 30 K. An electronic DC-DC converter was built in order to control the energy flow in and out of the superconducting coil. The converter consists of a MOS transistor bridge switching at a 80 kHz frequency and controlled with standard Pulse Width Modulation (PWM) techniques. The system was tested using a 30 V squared wave power supply as bridge input voltage. The coil current, the bridge input and output voltages were recorded simultaneously. Using a 10 A setpoint current in the superconducting coil, the whole system (coil + DC-DC converter) can provide a stable output voltage showing uninterruptible power supply (UPS) capabilities over 1 s. © 2006 IOP Publishing Ltd.

Electromagnetic-thermal design optimization of the brushless doubly fed induction generator

In view of its special features, the brushless doubly fed induction generator (BDFIG) shows high potentials to be employed as a variable-speed drive or wind generator. However, the machine suffers from low efficiency and power factor and also high level of noise and vibration due to spatial harmonics. These harmonics arise mainly from rotor winding configuration, slotting effects, and saturation. In this paper, analytical equations are derived for spatial harmonics and their effects on leakage flux, additional loss, noise, and vibration. Using the derived equations and an electromagnetic-thermal model, a simple design procedure is presented, while the design variables are selected based on sensitivity analyses. A multiobjective optimization method using an imperialist competitive algorithm as the solver is established to maximize efficiency, power factor, and power-to-weight ratio, as well as to reduce rotor spatial harmonic distortion and voltage regulation simultaneously. Several constraints on dimensions, magnetic flux densities, temperatures, vibration level, and converter voltage and rating are imposed to ensure feasibility of the designed machine. The results show a significant improvement in the objective function. Finally, the analytical results of the optimized structure are validated using finite-element method and are compared to the experimental results of the D180 frame size prototype BDFIG. © 1982-2012 IEEE.

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.

Voltage sensing buck converter-based technique for maximum photovoltaic solar energy delivery

A voltage sensing buck converter-based technique for maximum solar power delivery to a load is presented. While retaining the features and advantages of the incremental conductance algorithm, this technique is more desirable because of single sensor use. The technique operates by maximising power at the buck converter output instead of the input.

Increasing the open-circuit voltage of photoprotein-based photoelectrochemical cells by manipulation of the vacuum potential of the electrolytes.

The innately highly efficient light-powered separation of charge that underpins natural photosynthesis can be exploited for applications in photoelectrochemistry by coupling nanoscale protein photoreaction centers to man-made electrodes. Planar photoelectrochemical cells employing purple bacterial reaction centers have been constructed that produce a direct current under continuous illumination and an alternating current in response to discontinuous illumination. The present work explored the basis of the open-circuit voltage (V(OC)) produced by such cells with reaction center/antenna (RC-LH1) proteins as the photovoltaic component. It was established that an up to ~30-fold increase in V(OC) could be achieved by simple manipulation of the electrolyte connecting the protein to the counter electrode, with an approximately linear relationship being observed between the vacuum potential of the electrolyte and the resulting V(OC). We conclude that the V(OC) of such a cell is dependent on the potential difference between the electrolyte and the photo-oxidized bacteriochlorophylls in the reaction center. The steady-state short-circuit current (J(SC)) obtained under continuous illumination also varied with different electrolytes by a factor of ~6-fold. The findings demonstrate a simple way to boost the voltage output of such protein-based cells into the hundreds of millivolts range typical of dye-sensitized and polymer-blend solar cells, while maintaining or improving the J(SC). Possible strategies for further increasing the V(OC) of such protein-based photoelectrochemical cells through protein engineering are discussed.

Modeling turn-off voltage rise in SOI LIGBT

The behavior of the drain voltage rise of the Lateral IGBT during inductive turn-off is studied in detail. Numerical simulations show that, if compared with the well known vertical IGBT, the Lateral IGBT presents a differences in the on-state stored charge and in the growth of the depleted region that result in a different drain voltage rise. In this paper a complete model for the voltage rise is devised through an accurate calculation of the equivalent output capacitance. The model is in excellent agreement with two-dimensional simulations. Further, the paper shows that previously proposed models, which targeted the vertical IGBT, are not adequate for the description of the turn-off voltage rise in the Lateral IGBT. © Springer Science + Business Media LLC 2006.