Investigation into IGBT dV/dt during turn-off and its temperature dependence

In many power converter applications, particularly those with high variable loads, such as traction and wind power, condition monitoring of the power semiconductor devices in the converter is considered desirable. Monitoring the device junction temperature in such converters is an essential part of this process. In this paper, a method for measuring the insulated gate bipolar transistor (IGBT) junction temperature using the collector voltage dV/dt at turn-OFF is outlined. A theoretical closed-form expression for the dV/dt at turn-OFF is derived, closely agreeing with experimental measurements. The role of dV/dt in dynamic avalanche in high-voltage IGBTs is also discussed. Finally, the implications of the temperature dependence of the dV/dt are discussed, including implementation of such a temperature measurement technique. © 2006 IEEE.

Practical deployment of the brushless doubly-fed machine in a medium scale wind turbine

The Brushless Doubly-Fed Machine (BDFM) is a brushless electrical generator which allows variable speed operation with a power converter rated at only a fraction of the machine rating. This paper details an example implementation of the BDFM in a medium-scale wind turbine. Details of a simplified design procedure based on electrical and magnetic loadings are given along with the results of tests on the manufactured machine. These show that a BDFM of the scale works as expected but that the 4/8 BDFM chosen was slower and thus larger than the turbine's original induction machine. The implementation of the turbine system is discussed, including the vector-based control scheme that ensures the BDFM operates at a demanded speed and the Maximum Power Point Tracking (MPPT) scheme that selects the rotor speed that extracts the most power from the incident wind conditions.

Design of brushless doubly-fed machines based: On magnetic circuit modeling

This paper proposes a magnetic circuit model (MCM) for the design of a brushless doubly-fed machine (BDFM). The BDFM possesses advantages in terms of high reliability and reduced gearbox stages, and it requires a fractionally-rated power converter. This makes it suitable for utilization in offshore wind turbines. It is difficult for conventional design methods to calculate the flux in the stator because the two sets of stator windings, which have different pole number, form a complex flux pattern which is not easily determined using common analytical approaches. However, it is advantageous to predict the flux density in the teeth and air-gap at the initial design stage for sizing purposes without recourse finite element analysis. Therefore a magnetic circuit model is developed in this paper to calculate the flux density. A BDFM is used as a case study with FEA validation. © 1965-2012 IEEE.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Single sensor boost converter-based maximum power point tracking algorithms

Two new maximum power point tracking algorithms are presented: the input voltage sensor, and duty ratio maximum power point tracking algorithm (ViSD algorithm); and the output voltage sensor, and duty ratio maximum power point tracking algorithm (VoSD algorithm). The ViSD and VoSD algorithms have the features, characteristics and advantages of the incremental conductance algorithm (INC); but, unlike the incremental conductance algorithm which requires two sensors (the voltage sensor and current sensor), the two algorithms are more desirable because they require only one sensor: the voltage sensor. Moreover, the VoSD technique is less complex; hence, it requires less computational processing. Both the ViSD and the VoSD techniques operate by maximising power at the converter output, instead of the input. The ViSD algorithm uses a voltage sensor placed at the input of a boost converter, while the VoSD algorithm uses a voltage sensor placed at the output of a boost converter. © 2011 IEEE.

High-current adaptive impedance matching in narrowband power-line communication systems

This paper proposes a high current impedance matching method for narrowband power-line communication (NPLC) systems. The impedance of the power-line channel is time and location variant; therefore, coupling circuitry and the channel are not usually matched. This not only results in poor signal integrity at the receiving end, but also leads to a higher transmission power requirement to secure the communication process. To offset this negative effect, a high-current adaptive impedance circuit to enable impedance matching in power-line networks is reported. The approach taken is to match the channel impedance of N-PLC systems is based on the General Impedance Converter (GIC). In order to achieve high current a special coupler in which the inductive impedance can be altered by adjusting a microcontroller controlled digital resistor is demonstrated. It is shown that the coupler works well with heavy load current in power line networks. It works in both low and high transmitting current modes, a current as high as 760 mA has been obtained. Besides, compared with other adaptive impedance couplers, the advantages include higher matching resolution and a simple control interface. Experimental results are presented to demonstrate the operation of the coupler. © 2011 IEEE.

HVIC switch for high-frequency power converters

A high voltage integrated circuit (HVIC) switch designed as a building block for power converters operating up to 13.56 MHz from off-line voltages is presented. A CMOS-compatible, 500 V power device process is used to integrate control circuitry with a high-speed MOS gate driver and high voltage lateral power MOSFET. Fabrication of the HVIC switches has proceeded in two stages. The first batch of devices showed switching times of less than 5 ns for the power switch and good high frequency performance of a level-shifter for driving half bridge converters. In the second phase, a switch that monolithically integrates all the elements required to form a complete high-frequency converter has been designed.

Wavelength conversion based on an integrated semiconductor optical amplifier/DFB laser at 10 Gb/s with low input power

A study of the relative performance of an integrated semiconductor optical amplifier (SOA)/distributed feedback laser wavelength converter that can operate with negative penalties at 10 Gb/s rates is conducted. It is found that reduction of more than 25 times in required input powers are achieved when compared with laser or SOA converters.

A fully integrated 660 MHz low-swing energy-recycling DC-DC converter

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

A 4 GHz non-resonant clock driver with inductor-assisted energy return to power grid

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.