Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

Evaluating the impacts of iteration on PD processes by transforming task network models into System Dynamics models

Iteration is unavoidable in the design process and should be incorporated when planning and managing projects in order to minimize surprises and reduce schedule distortions. However, planning and managing iteration is challenging because the relationships between its causes and effects are complex. Most approaches which use mathematical models to analyze the impact of iteration on the design process focus on a relatively small number of its causes and effects. Therefore, insights derived from these analytical models may not be robust under a broader consideration of potential influencing factors. In this article, we synthesize an explanatory framework which describes the network of causes and effects of iteration identified from the literature, and introduce an analytic approach which combines a task network modeling approach with System Dynamics simulation. Our approach models the network of causes and effects of iteration alongside the process architecture which is required to analyze the impact of iteration on design process performance. We show how this allows managers to assess the impact of changes to process architecture and to management levers which influence iterative behavior, accounting for the fact that these changes can occur simultaneously and can accumulate in non-linear ways. We also discuss how the insights resulting from this analysis can be visualized for easier consumption by project participants not familiar with simulation methods. Copyright © 2010 by ASME.