Floating-body SOI memory: Concepts, physics and challenges

We present an overview of the single-transistor memory cells (lT-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling. ©The Electrochemical Society.

Estimating and Enhancing the Yield of Tuneling SRAM Cells by Simulation

As a novel implementation of the static random access memory (SRAM), the tunneling SRAM (TSRAM) uses the negative differential resistance of tunnel diodes (TD’s) and potentially offers considerable improvements in both standby power dissipation and integration density compared to the conventional CMOS SRAM. TSRAM has not yet been realized with a useful bit capacity mainly because the level of uniformity required of the nanoscale TD’s has been demanding and difficult to achieve. In this letter, we propose a Monte Carlo approach for estimating the yield of TSRAM cells and show that by optimizing the cell’s external circuit parameters, we can relax the allowable tolerance of a key device parameter of a resonant-TD-(RTD) based cell by three times.