6 resultados para MEMORY PERFORMANCE

em Cambridge University Engineering Department Publications Database


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A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s. © 2014 AIP Publishing LLC.

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The investigation of an inverted hybrid digital/ optical VanderLugt type correlator based on a holographic memory is reported in this paper. A set of reference templates is stored in a photorefractive crystal (PRC) by angular hologram multiplexing. In the filter plane, a phase-modulating liquid crystal television (LCTV) serves as a phase-only input device. During the recognition process, which is based on the pure phase correlation, the reference templates are correlated sequentially with the input object. This correlator shows high sensitivity to object rotation, sharp correlation peaks, high light efficiency, and is fully shift-invariant in spite of the PRC thickness. The influences of the LCTV on the performance of the system are discussed and experimental results are shown.

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We present an overview of the single-transistor memory cells (lT-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling. ©The Electrochemical Society.

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Performance on visual working memory tasks decreases as more items need to be remembered. Over the past decade, a debate has unfolded between proponents of slot models and slotless models of this phenomenon (Ma, Husain, Bays (Nature Neuroscience 17, 347-356, 2014). Zhang and Luck (Nature 453, (7192), 233-235, 2008) and Anderson, Vogel, and Awh (Attention, Perception, Psychophys 74, (5), 891-910, 2011) noticed that as more items need to be remembered, "memory noise" seems to first increase and then reach a "stable plateau." They argued that three summary statistics characterizing this plateau are consistent with slot models, but not with slotless models. Here, we assess the validity of their methods. We generated synthetic data both from a leading slot model and from a recent slotless model and quantified model evidence using log Bayes factors. We found that the summary statistics provided at most 0.15 % of the expected model evidence in the raw data. In a model recovery analysis, a total of more than a million trials were required to achieve 99 % correct recovery when models were compared on the basis of summary statistics, whereas fewer than 1,000 trials were sufficient when raw data were used. Therefore, at realistic numbers of trials, plateau-related summary statistics are highly unreliable for model comparison. Applying the same analyses to subject data from Anderson et al. (Attention, Perception, Psychophys 74, (5), 891-910, 2011), we found that the evidence in the summary statistics was at most 0.12 % of the evidence in the raw data and far too weak to warrant any conclusions. The evidence in the raw data, in fact, strongly favored the slotless model. These findings call into question claims about working memory that are based on summary statistics.