Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Dasher - A data entry interface using continuous gestures and language models

Existing devices for communicating information to computers are bulky, slow to use, or unreliable. Dasher is a new interface incorporating language modelling and driven by continuous two-dimensional gestures, e.g. a mouse, touchscreen, or eye-tracker. Tests have shown that this device can be used to enter text at a rate of up to 34 words per minute, compared with typical ten-finger keyboard typing of 40-60 words per minute. Although the interface is slower than a conventional keyboard, it is small and simple, and could be used on personal data assistants and by motion-impaired computer users.

Patterning and detailed study of human hNT astrocytes on parylene-C/silicon dioxide substrates to the single cell level.

It is estimated that the adult human brain contains 100 billion neurons with 5-10 times as many astrocytes. Although it has been generally considered that the astrocyte is a simple supportive cell to the neuron, recent research has revealed new functionality of the astrocyte in the form of information transfer to neurons of the brain. In our previous work we developed a protocol to pattern the hNT neuron (derived from the human teratocarcinoma cell line (hNT)) on parylene-C/SiO(2) substrates. In this work, we report how we have managed to pattern hNT astrocytes, on parylene-C/SiO(2) substrates to single cell resolution. This article disseminates the nanofabrication and cell culturing steps necessary for the patterning of such cells. In addition, it reports the necessary strip lengths and strip width dimensions of parylene-C that encourage high degrees of cellular coverage and single cell isolation for this cell type. The significance in patterning the hNT astrocyte on silicon chip is that it will help enable single cell and network studies into the undiscovered functionality of this interesting cell, thus, contributing to closer pathological studies of the human brain.