Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

A 4 GHz non-resonant clock driver with inductor-assisted energy return to power grid

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region. © 2006 IEEE.

Americium nuclear battery for space power applications

The work presents simplified242mAm fueled nuclear battery concept design featuring direct fission products energy conversion and passive heat rejection. The performed calculations of power conversion efficiency under thermal and nuclear design constraints showed that 14 W/kg power density can be achieved, which corresponds to conversion efficiency of about 6%. Total power of the battery scales linearly with its surface area. 144 kW of electric power can be produced by a nuclear battery with an external radius of about 174 cm and total mass of less than 10300 kg. The mass of242m Am fuel for such a system is 3200 gram.

200V superjunction lateral IGBT fabricated on partial SOI

A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process. © 2013 IEEE.

Analytical model for the 3D-RESURF effect

This paper presents an analytical model for the determination of the basic breakdown properties of three-dimensional (3D)-RESURF/CoolMOS/super junction type structures. To account for the two-dimensional (2D) effect of the 3D-RESURF action, 2D models of the electric field distribution are developed. Based on these, expressions are derived for the breakdown voltage as a function of doping concentration and physical dimensions. In addition to cases where the drift regions are fully depleted, the model developed is also applicable to situations involving drift regions which are almost depleted. Accuracy of the analytical approach is verified by comparison with numerical results obtained from the MEDICI device simulator.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Experimental study on an SFCL using series-connected YBCO thin films

Superconducting Fault Current Limiters (SFCLs) are able to reduce fault currents to an acceptable value, reducing potential mechanical and thermal damage and allowing more flexibility in an electric power system's design. Due to limitations in current YBCO thin film manufacturing techniques, it is necessary to connect a number of thin films in different series and parallel configurations in order to realise a practical SFCL for electric power system applications. The amount of resistance generated (i.e. the degree of current limitation), the characteristics of the S-N transition, and the time at which they operate is different depending on their comparative characteristics. However, it is desirable for series-connected thin films to have an operating time difference as small as possible to avoid placing an excess burden on certain thin films. The role of a parallel resistance, along with the influence of thin film characteristics, such as critical current (Ic), are discussed in regards to the design of SFCLs using YBCO thin films. © 2008 IOP Publishing Ltd.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

The lateral superjunction PSOI LIGBT and LDMOSFET

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology. © 2012 IEEE.