Active Voltage Control on series connection of IGBTs and diode recovery optimization

In this paper an Active Voltage Control (AVC) technique is presented, for series connection of insulated-gate-bipolar-transistors (IGBT) and control of diode recovery. The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. Another key advantage for AVC is that by changing the reference signal at turn-on, the diode recovery can be optimised. © 2010 IEEE.

IGBT series connection under active voltage control

In this paper an Active Voltage Control (AVC) technique is presented, for series connection of insulated-gate-bipolar-transistors (IGBT) and control of diode recovery. The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. For the static voltage balancing, the AVC technique can clamp the highest collector-to-emitter voltage to a pre-set clamping voltage level. By selecting the value of the clamping voltage, the difference among series connected IGBTs can be controlled in an accepted range. Another key advantage for AVC is that by changing the reference signal at turn-on, the diode recovery can be optimized. © 2011 EPE Association - European Power Electr.

Series-connected IGBTs using active voltage control technique

With series insulated-gate bipolar transistor (IGBT) operation, well-matched gate drives will not ensure balanced dynamic voltage sharing between the switching devices. Rather, it is IGBT parasitic capacitances, mainly gate-to-collector capacitance Cgc, that dominate transient voltage sharing. As Cgc is collector voltage dependant and is significantly larger during the initial turn-off transition, it dominates IGBT dynamic voltage sharing. This paper presents an active control technique for series-connected IGBTs that allows their dynamic voltage transition dV\ce/dt to adaptively vary. Both switch ON and OFF transitions are controlled to follow a predefined dVce/dt. Switching losses associated with this technique are minimized by the adaptive dv /dt control technique incorporated into the design. A detailed description of the control circuits is presented in this paper. Experimental results with up to three series devices in a single-ended dc chopper circuit, operating at various low voltage and current levels, are used to illustrate the performance of the proposed technique. © 2012 IEEE.

IGBT series connection under Active Voltage Control with temporary clamp

This paper presents the use of an Active Voltage Control (AVC) technique for balancing the voltages in a series connection of Insulated Gate Bipolar Transistors (IGBTs). The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. For the static voltage balancing, a temporary clamp technique is introduced. The temporary clamp technique clamps the collector-emitter voltage of all the series connected IGBTs at the ideal voltage so that the IGBTs will share the voltage evenly. © 2012 IEEE.

Dynamic analysis of the brushless doubly-fed induction generator during symmetrical three-phase voltage dips

The Brushless Doubly-Fed Induction Generator (BDFIG) shows commercial promise as replacement for doublyfed slip-ring generators for wind power applications by offering reduced capital and operational costs due to its brushless operation. In order to facilitate its commercial deployment, the capabilities of the BDFIG system to comply with grid code requirements have to be assessed. This paper, for the first time, studies the performance of the BDFIG under grid fault ride-through and presents the dynamic behaviour of the machine during three-phase symmetrical voltage dips. Both full and partial voltage dips are studied using a vector model. Simulation and experimental results are provided for a 180 frame BDFIG.

Numerical analysis of the current and voltage sharing issues for resistive fault current limiter using YBCO coated conductors

YBaCuO-coated conductors offer great potential in terms of performance and cost-saving for superconducting fault current limiter (SFCL). A resistive SFCL based on coated conductors can be made from several tapes connected in parallel or in series. Ideally, the current and voltage are shared uniformly by the tapes when quench occurs. However, due to the non-uniformity of property of the tapes and the relative positions of the tapes, the currents and the voltages of the tapes are different. In this paper, a numerical model is developed to investigate the current and voltage sharing problem for the resistive SFCL. This model is able to simulate the dynamic response of YBCO tapes in normal and quench conditions. Firstly, four tapes with different Jc 's and n values in E-J power law are connected in parallel to carry the fault current. The model demonstrates how the currents are distributed among the four tapes. These four tapes are then connected in series to withstand the line voltage. In this case, the model investigates the voltage sharing between the tapes. Several factors that would affect the process of quenches are discussed including the field dependency of Jc, the magnetic coupling between the tapes and the relative positions of the tapes. © 2010 IEEE.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.