Switched reluctance motor drive without direct rotor position sensing

A closed-loop control technique based on monitoring phase current risetime for switched reluctance (SR) motors without direct rotor-position sensors has been studied and implemented successfully. In this technique the variation in incremental phase inductance in a SR motor is used to detect rotor position. A control circuit for current-waveform-based rotor position detection has been implemented using hard-wire digital circuits. Torque-speed and system-efficiency characteristics resulting from the application of the method to a 4-kW, four-phase SR motor with an IGBT drive are presented.

Fixed-lag blind equalization and sequence estimation in digital communications systems using sequential importance sampling

We present methods for fixed-lag smoothing using Sequential Importance sampling (SIS) on a discrete non-linear, non-Gaussian state space system with unknown parameters. Our particular application is in the field of digital communication systems. Each input data point is taken from a finite set of symbols. We represent transmission media as a fixed filter with a finite impulse response (FIR), hence a discrete state-space system is formed. Conventional Markov chain Monte Carlo (MCMC) techniques such as the Gibbs sampler are unsuitable for this task because they can only perform processing on a batch of data. Data arrives sequentially, so it would seem sensible to process it in this way. In addition, many communication systems are interactive, so there is a maximum level of latency that can be tolerated before a symbol is decoded. We will demonstrate this method by simulation and compare its performance to existing techniques.

GSPS photonic analogue to digital conversion system using broadband continuous wave source

An 80 GSPS photonic ADC system is demonstrated, using broadband MLL and dispersive fibre to form a continuous waveform with time-wavelength mapping, and AWG to channelise. Tests are carried out for RF signals up to 10GHz. © 2005 Optical Society of America.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.