Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

Analysis of switched capacitor DC-DC step down converter

A 5V/1 V Switched Capacitor (SC) dc-dc converter designed for a 0.18μm CMOS process is analysed in detail, in this paper. Analytical equations are derived for the voltages and currents through the main components of the SC converter. The model includes switches, capacitors, equivalent series resistances and the load. The switches in the converter are represented by MOSFETs in the UMC 0.18μm CMOS process. The impact of system parameters on output voltage ripple are studied using the analytical expressions.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.