Advanced DC link capacitor technology application for a stiff voltage-source inverter

Problem of DC link size in a stiff voltage-source inverter for electric drive is described in the paper. Advantages of advanced film capacitor technology over conventional one for DC link application are reviewed. Conventional DC link capacitor selection methods are questioned in view of advanced capacitor technology utilization in stiff voltage-source inverter. For capacitor selection maximum ripple rms current point is shown. DC link ripple current spectrum analysis under modern PWM techniques is presented. Some capacitor selection recommendations are given. The analysis has been aided greatly by computer modeling in PSpice. ©2005 IEEE.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

5.4-MHz single-crystal silicon wine glass mode disk resonator with quality factor of 2 million

This paper reports the design and electrical characterization of a micromechanical disk resonator fabricated in single crystal silicon using a foundry SOI micromachining process. The microresonator has been selectively excited in the radial extensional and the wine glass modes by reversing the polarity of the DC bias voltage applied on selected drive electrodes around the resonant structure. The quality factor of the resonator vibrating in the radial contour mode was 8000 at a resonant frequency of 6.34 MHz at pressure below 10 mTorr vacuum. The highest measured quality factor of the resonator in the wine glass resonant mode was 1.9 × 106 using a DC bias voltage of 20 V at about the same pressure in vacuum; the resonant frequency was 5.43 MHz and the lowest motional resistance measured was approximately 17 kΩ using a DC bias voltage of 60 V applied across 2.7 μm actuation gaps. This corresponds to a resonant frequency-quality factor (f-Q) product of 1.02 × 1013, among the highest reported for single crystal silicon microresonators, and on par with the best quartz crystal resonators. The quality factor for the wine glass mode in air was approximately 10,000. © 2009 Elsevier B.V. All rights reserved.

Binary excitation of a high-Q bulk acoustic microresonator by actuation polarity inversion

We present a technique for independently exciting two resonant modes of vibration in a single-crystal silicon bulk mode microresonator using the same electrode configuration through control of the polarity of the DC actuation voltage. Applications of this technique may include built-in temperature compensation by the simultaneous selective excitation of two closely spaced modes that may have different temperature coefficients of resonant frequency. The technique is simple and requires minimum circuit overhead for implementation. The technique is implemented on square plate resonators with quality factors as high as 3.06 × 106. Copyright © 2008 by ASME.

Low loss HF band SOI wine glass bulk mode capacitive square-plate resonator

This paper reports on the design and electrical characterization of a single crystal silicon micromechanical square-plate resonator. The microresonator has been excited in the anti-symmetrical wine glass mode at a resonant frequency of 5.166 MHz and exhibits an impressive quality factor (Q) of 3.7 × 106 at a pressure of 33 mtorr. The device has been fabricated in a commercial foundry process. An associated motional resistance of approximately 50 kΩ using a dc bias voltage of 60 V is measured for a transduction gap of 2 νm due to the ultra-high Q of the resonator. This result corresponds to a frequency-Q product of 1.9 × 1013, the highest reported for a fundamental mode single-crystal silicon resonator and on par with some of the best quartz crystal resonators. The results are indicative of the superior performance of silicon as a mechanical material, and show that the wine glass resonant mode is beneficial for achieving high quality factors allowed by the material limit. © 2009 IOP Publishing Ltd.

Electromagnetic-thermal design optimization of the brushless doubly fed induction generator

In view of its special features, the brushless doubly fed induction generator (BDFIG) shows high potentials to be employed as a variable-speed drive or wind generator. However, the machine suffers from low efficiency and power factor and also high level of noise and vibration due to spatial harmonics. These harmonics arise mainly from rotor winding configuration, slotting effects, and saturation. In this paper, analytical equations are derived for spatial harmonics and their effects on leakage flux, additional loss, noise, and vibration. Using the derived equations and an electromagnetic-thermal model, a simple design procedure is presented, while the design variables are selected based on sensitivity analyses. A multiobjective optimization method using an imperialist competitive algorithm as the solver is established to maximize efficiency, power factor, and power-to-weight ratio, as well as to reduce rotor spatial harmonic distortion and voltage regulation simultaneously. Several constraints on dimensions, magnetic flux densities, temperatures, vibration level, and converter voltage and rating are imposed to ensure feasibility of the designed machine. The results show a significant improvement in the objective function. Finally, the analytical results of the optimized structure are validated using finite-element method and are compared to the experimental results of the D180 frame size prototype BDFIG. © 1982-2012 IEEE.

Analysis of switched capacitor DC-DC step down converter

A 5V/1 V Switched Capacitor (SC) dc-dc converter designed for a 0.18μm CMOS process is analysed in detail, in this paper. Analytical equations are derived for the voltages and currents through the main components of the SC converter. The model includes switches, capacitors, equivalent series resistances and the load. The switches in the converter are represented by MOSFETs in the UMC 0.18μm CMOS process. The impact of system parameters on output voltage ripple are studied using the analytical expressions.

A fully integrated 660 MHz low-swing energy-recycling DC-DC converter

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.