Overview and status of bottom-up silicon nanowire electronics

This review summarises the recent advances in the field of silicon nanowire electronics from bottom-up assembled materials. The aim is to draw a comparison between bottom-up and top-down approaches, examining respective achievements and evaluating advantages and disadvantages of each methodology. Existing techniques for synthesis and doping are discussed to provide the framework in which practical electronic applications can be developed. Next, key device categories are reviewed, emphasising current challenges and proposed solutions. Finally, field perspectives are outlined. © 2012 Elsevier Ltd.

Scanning gate microscopy of current-annealed single layer graphene

We have used scanning gate microscopy to explore the local conductivity of a current-annealed graphene flake. A map of the local neutrality point (NP) after annealing at low current density exhibits micron-sized inhomogeneities. Broadening of the local e-h transition is also correlated with the inhomogeneity of the NP. Annealing at higher current density reduces the NP inhomogeneity, but we still observe some asymmetry in the e-h conduction. We attribute this to a hole-doped domain close to one of the metal contacts combined with underlying striations in the local NP. © 2010 American Institute of Physics.