157 resultados para BEAM EPITAXIAL GAAS

em Cambridge University Engineering Department Publications Database


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We demonstrate vertically aligned epitaxial GaAs nanowires of excellent crystallographic quality and optimal shape, grown by Au nanoparticle-catalyzed metalorganic chemical vapor deposition. This is achieved by a two-temperature growth procedure, consisting of a brief initial high-temperature growth step followed by prolonged growth at a lower temperature. The initial high-temperature step is essential for obtaining straight, vertically aligned epitaxial nanowires on the (111)B GaAs substrate. The lower temperature employed for subsequent growth imparts superior nanowire morphology and crystallographic quality by minimizing radial growth and eliminating twinning defects. Photoluminescence measurements confirm the excellent optical quality of these two-temperature grown nanowires. Two mechanisms are proposed to explain the success of this two-temperature growth process, one involving Au nanoparticle-GaAs interface conditions and the other involving melting-solidification temperature hysteresis of the Au-Ga nanoparticle alloy.

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The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

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Seeded zone-melt recrystallization using a dual electron beam system has been performed on silicon-on-insulator material, which was prepared with single-crystal silicon filling of the seed windows by selective epitaxial growth. The crystal quality has been assessed by a variety of microscopic techniques, and it is shown that single-crystal films 0.5-1.0 μm thick over 1.0 μm of isolating oxide may be prepared by this method. These films have considerably less lateral variation in thickness than standard material, in which the windows are not so filled. The filling method is suitable for both single- and multiple-layer silicon-on-insulator, and gives the advantages of excellent layer uniformity after recrystallization and improved planarity of the whole chip structure. Experiments using various amounts of seed window filling have shown that the lateral variations of silicon film thickness seen in unplanarized material are due to stress relief in the cap oxide when the silicon film is molten, rather than the effect previously postulated in which they were assumed to be due to the contraction of silicon on melting.

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Electron tunnelling through semiconductor tunnel barriers is exponentially sensitive to the thickness of the barrier layer, and in the most common system, the AlAs tunnel barrier in GaAs, a one monolayer variation in thickness results in a 300% variation in the tunnelling current for a fixed bias voltage. We use this degree of sensitivity to demonstrate that the level of control at 0.06 monolayer can be achieved in the growth by molecular beam epitaxy, and the geometrical variation of layer thickness across a wafer at the 0.01 monolayer level can be detected.

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Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metal-organic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH 3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance. © 2012 IOP Publishing Ltd.

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The growth of epitaxial Ge nanowires is investigated on (100), (111) B and (110) GaAs substrates in the growth temperature range from 300 to 380 °C. Unlike epitaxial Ge nanowires on Ge or Si substrates, Ge nanowires on GaAs substrates grow predominantly along the [Formula: see text] direction. Using this unique property, vertical [Formula: see text] Ge nanowires epitaxially grown on GaAs(110) surface are realized. In addition, these Ge nanowires exhibit minimal tapering and uniform diameters, regardless of growth temperatures, which is an advantageous property for device applications. Ge nanowires growing along the [Formula: see text] directions are particularly attractive candidates for forming nanobridge devices on conventional (100) surfaces.

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In this paper, we demonstrate the key issues of axial nanowire heterostructures, such as, the fundamental criteria for formation and failure of axial nanowire heterostructures via vapor-liquid-solid mechanism and lateral misfit strain relaxation in these structures. We show the failure of axial nanowire heterostructures by growing InAs axially on GaAs nanowires, and the lateral misfit strain relaxation by axial growth of GaSb on GaAs nanowires. © 2008 IEEE.

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We report a two-temperature procedure for the growth of GaAs nanowires by metalorganic chemical vapour deposition. An initial high temperature step affords effective nucleation and promotes epitaxial growth of straight (111)B-oriented nanowires. Lower temperatures are employed subsequently, to minimise nanowire tapering during growth. © 2006 IEEE.