Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Efficient InGaAsP/InP multiple quantum well optical phase modulator for the 1.5-1.55μm fiber band

We report an InGaAsP/InP MQW phase modulator operating over the entire 1.55μm fiber band with high phase modulation efficiency and low loss modulation. The spectral dependence of the electro-refraction in a MQW structure is measured for the first time.

1.55-μm VCSEL transmission performance up to 20 Gb/s for access networks

We experimentally demonstrate for the first time 1.55μm vertical-cavity surface-emitting laser (VCSEL) transmission over 6.5 km single mode fiber (SMF) at 20 Gb/s for optical access networks. Characterization of the device is also investigated. © 2009 IEEE.